target/i386: Set 2-NaN propagation rule explicitly
Set the NaN propagation rule explicitly for the float_status words used in the x86 target. This is a no-behaviour-change commit, so we retain the existing behaviour of using the x87-style "prefer QNaN over SNaN, then prefer the NaN with the larger significand" for MMX and SSE. This is however not the documented hardware behaviour, so we leave a TODO note about what we should be doing instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241025141254.2141506-16-peter.maydell@linaro.org
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@ -405,7 +405,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
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|| defined(TARGET_TRICORE) || defined(TARGET_ARM) || defined(TARGET_MIPS) \
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|| defined(TARGET_LOONGARCH64) || defined(TARGET_HPPA) \
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|| defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_M68K) \
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|| defined(TARGET_SPARC) || defined(TARGET_XTENSA)
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|| defined(TARGET_SPARC) || defined(TARGET_XTENSA) \
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|| defined(TARGET_I386)
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g_assert_not_reached();
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#else
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rule = float_2nan_prop_x87;
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@ -7200,6 +7200,10 @@ static void x86_cpu_reset_hold(Object *obj, ResetType type)
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memset(env, 0, offsetof(CPUX86State, end_reset_fields));
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if (tcg_enabled()) {
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cpu_init_fp_statuses(env);
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}
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env->old_exception = -1;
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/* init to reset state */
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@ -2614,6 +2614,9 @@ static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
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int get_pg_mode(CPUX86State *env);
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/* fpu_helper.c */
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/* Set all non-runtime-variable float_status fields to x86 handling */
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void cpu_init_fp_statuses(CPUX86State *env);
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void update_fp_status(CPUX86State *env);
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void update_mxcsr_status(CPUX86State *env);
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void update_mxcsr_from_sse_status(CPUX86State *env);
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@ -135,6 +135,46 @@ static void fpu_set_exception(CPUX86State *env, int mask)
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}
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}
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void cpu_init_fp_statuses(CPUX86State *env)
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{
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/*
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* Initialise the non-runtime-varying fields of the various
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* float_status words to x86 behaviour. This must be called at
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* CPU reset because the float_status words are in the
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* "zeroed on reset" portion of the CPU state struct.
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* Fields in float_status that vary under guest control are set
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* via the codepath for setting that register, eg cpu_set_fpuc().
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*/
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/*
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* Use x87 NaN propagation rules:
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* SNaN + QNaN => return the QNaN
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* two SNaNs => return the one with the larger significand, silenced
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* two QNaNs => return the one with the larger significand
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* SNaN and a non-NaN => return the SNaN, silenced
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* QNaN and a non-NaN => return the QNaN
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*
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* If we get down to comparing significands and they are the same,
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* return the NaN with the positive sign bit (if any).
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*/
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set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
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/*
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* TODO: These are incorrect: the x86 Software Developer's Manual vol 1
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* section 4.8.3.5 "Operating on SNaNs and QNaNs" says that the
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* "larger significand" behaviour is only used for x87 FPU operations.
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* For SSE the required behaviour is to always return the first NaN,
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* which is float_2nan_prop_ab.
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*
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* mmx_status is used only for the AMD 3DNow! instructions, which
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* are documented in the "3DNow! Technology Manual" as not supporting
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* NaNs or infinities as inputs. The result of passing two NaNs is
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* documented as "undefined", so we can do what we choose.
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* (Strictly there is some behaviour we don't implement correctly
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* for these "unsupported" NaN and Inf values, like "NaN * 0 == 0".)
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*/
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set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
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set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
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}
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static inline uint8_t save_exception_flags(CPUX86State *env)
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{
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uint8_t old_flags = get_float_exception_flags(&env->fp_status);
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