Miscellaneous bugfixes
-----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAloMXN0UHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNNAQf/e7/uT2tW7WNfamSOMYXswf0R6ak+ KjVSG+qiNsKaZzXmMFkhm4n0u1vCW0VGEQGRHr0MoSCyyfhupzLRHxfHi8SytqTf S6wqNtIbOK0L8bW+U5vzADks33UCuuUNlVZeOAkEPaXiLlgxmBoHfyoXkIGemJc2 epx5x22rloNQLaBoL7FGmAkQhQCSJg19hAtRLo0tkryCwBZ9P6a1K0aNAHU2RFaB LgRFcxwduwTydsHRYeQ8J7YR0fERle01QUB8y9tlOc8/d2x9yRPBWhPHwscKMv6I JwM0c2Mnw6Yqbwyj7snWty7epgUcHWrOVnZnaIpNW9Z8m/wgz28oZ3a09w== =6wL6 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging Miscellaneous bugfixes # gpg: Signature made Wed 15 Nov 2017 15:27:25 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: fix scripts/update-linux-headers.sh here document exec: Do not resolve subpage in mru_section util/stats64: Fix min/max comparisons cpu-exec: avoid cpu_exec_nocache infinite loop with record/replay cpu-exec: don't overwrite exception_index vhost-user-scsi: add missing virtqueue_size param target-i386: adds PV_TLB_FLUSH CPUID feature bit thread-posix: fix qemu_rec_mutex_trylock macro Makefile: simpler/faster "make help" ioapic/tracing: Remove last DPRINTFs Enable 8-byte wide MMIO for 16550 serial devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
62955e101e
2
Makefile
2
Makefile
@ -6,7 +6,7 @@ BUILD_DIR=$(CURDIR)
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# Before including a proper config-host.mak, assume we are in the source tree
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SRC_PATH=.
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UNCHECKED_GOALS := %clean TAGS cscope ctags docker docker-%
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UNCHECKED_GOALS := %clean TAGS cscope ctags docker docker-% help
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# All following code might depend on configuration variables
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ifneq ($(wildcard config-host.mak),)
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@ -470,7 +470,19 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
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static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
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{
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if (cpu->exception_index >= 0) {
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if (cpu->exception_index < 0) {
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#ifndef CONFIG_USER_ONLY
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if (replay_has_exception()
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&& cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
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/* try to cause an exception pending in the log */
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cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
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}
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#endif
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if (cpu->exception_index < 0) {
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return false;
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}
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}
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if (cpu->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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*ret = cpu->exception_index;
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@ -503,15 +515,6 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
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*ret = EXCP_INTERRUPT;
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return true;
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}
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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} else if (replay_has_exception()
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&& cpu->icount_decr.u16.low + cpu->icount_extra == 0) {
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/* try to cause an exception pending in the log */
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cpu_exec_nocache(cpu, 1, tb_find(cpu, NULL, 0, curr_cflags()), true);
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*ret = -1;
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return true;
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#endif
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}
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@ -522,6 +525,19 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
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TranslationBlock **last_tb)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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int32_t insns_left;
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/* Clear the interrupt flag now since we're processing
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* cpu->interrupt_request and cpu->exit_request.
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*/
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insns_left = atomic_read(&cpu->icount_decr.u32);
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atomic_set(&cpu->icount_decr.u16.high, 0);
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if (unlikely(insns_left < 0)) {
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/* Ensure the zeroing of icount_decr comes before the next read
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* of cpu->exit_request or cpu->interrupt_request.
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*/
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smp_mb();
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}
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if (unlikely(atomic_read(&cpu->interrupt_request))) {
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int interrupt_request;
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@ -594,7 +610,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
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if (unlikely(atomic_read(&cpu->exit_request)
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|| (use_icount && cpu->icount_decr.u16.low + cpu->icount_extra == 0))) {
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atomic_set(&cpu->exit_request, 0);
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if (cpu->exception_index == -1) {
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cpu->exception_index = EXCP_INTERRUPT;
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}
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return true;
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}
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@ -618,17 +636,14 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
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*last_tb = NULL;
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insns_left = atomic_read(&cpu->icount_decr.u32);
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atomic_set(&cpu->icount_decr.u16.high, 0);
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if (insns_left < 0) {
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/* Something asked us to stop executing chained TBs; just
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* continue round the main loop. Whatever requested the exit
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* will also have set something else (eg exit_request or
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* interrupt_request) which we will handle next time around
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* the loop. But we need to ensure the zeroing of icount_decr
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* comes before the next read of cpu->exit_request
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* or cpu->interrupt_request.
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* interrupt_request) which will be handled by
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* cpu_handle_interrupt. cpu_handle_interrupt will also
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* clear cpu->icount_decr.u16.high.
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*/
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smp_mb();
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return;
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}
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12
exec.c
12
exec.c
@ -410,22 +410,16 @@ static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
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{
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MemoryRegionSection *section = atomic_read(&d->mru_section);
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subpage_t *subpage;
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bool update;
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if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] &&
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section_covers_addr(section, addr)) {
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update = false;
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} else {
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if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
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!section_covers_addr(section, addr)) {
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section = phys_page_find(d, addr);
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update = true;
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atomic_set(&d->mru_section, section);
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}
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if (resolve_subpage && section->mr->subpage) {
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subpage = container_of(section->mr, subpage_t, iomem);
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section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
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}
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if (update) {
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atomic_set(&d->mru_section, section);
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}
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return section;
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}
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@ -1005,7 +1005,7 @@ static void serial_mm_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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SerialState *s = opaque;
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value &= ~0u >> (32 - (size * 8));
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value &= 255;
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serial_ioport_write(s, addr >> s->it_shift, value, 1);
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}
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@ -1014,16 +1014,22 @@ static const MemoryRegionOps serial_mm_ops[3] = {
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.read = serial_mm_read,
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.write = serial_mm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.max_access_size = 8,
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.impl.max_access_size = 8,
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},
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[DEVICE_LITTLE_ENDIAN] = {
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.read = serial_mm_read,
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.write = serial_mm_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.max_access_size = 8,
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.impl.max_access_size = 8,
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},
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[DEVICE_BIG_ENDIAN] = {
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.read = serial_mm_read,
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.write = serial_mm_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid.max_access_size = 8,
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.impl.max_access_size = 8,
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},
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};
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@ -35,15 +35,6 @@
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#include "hw/i386/x86-iommu.h"
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#include "trace.h"
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//#define DEBUG_IOAPIC
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#ifdef DEBUG_IOAPIC
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#define DPRINTF(fmt, ...) \
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do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define APIC_DELIVERY_MODE_SHIFT 8
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#define APIC_POLARITY_SHIFT 14
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#define APIC_TRIG_MODE_SHIFT 15
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@ -157,7 +148,7 @@ static void ioapic_set_irq(void *opaque, int vector, int level)
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* to GSI 2. GSI maps to ioapic 1-1. This is not
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* the cleanest way of doing it but it should work. */
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DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
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trace_ioapic_set_irq(vector, level);
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if (vector == 0) {
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vector = 2;
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}
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@ -290,11 +281,10 @@ ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
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}
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}
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}
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DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
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break;
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}
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trace_ioapic_mem_read(addr, size, val);
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trace_ioapic_mem_read(addr, s->ioregsel, size, val);
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return val;
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}
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@ -335,7 +325,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
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int index;
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addr &= 0xff;
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trace_ioapic_mem_write(addr, size, val);
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trace_ioapic_mem_write(addr, s->ioregsel, size, val);
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switch (addr) {
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case IOAPIC_IOREGSEL:
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@ -345,7 +335,6 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
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if (size != 4) {
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break;
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}
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DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
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@ -18,8 +18,9 @@ apic_mem_writel(uint64_t addr, uint32_t val) "0x%"PRIx64" = 0x%08x"
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ioapic_set_remote_irr(int n) "set remote irr for pin %d"
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ioapic_clear_remote_irr(int n, int vector) "clear remote irr for pin %d vector %d"
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ioapic_eoi_broadcast(int vector) "EOI broadcast for vector %d"
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ioapic_mem_read(uint8_t addr, uint8_t size, uint32_t val) "ioapic mem read addr 0x%"PRIx8" size 0x%"PRIx8" retval 0x%"PRIx32
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ioapic_mem_write(uint8_t addr, uint8_t size, uint32_t val) "ioapic mem write addr 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32
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ioapic_mem_read(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) "ioapic mem read addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" retval 0x%"PRIx32
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ioapic_mem_write(uint8_t addr, uint8_t regsel, uint8_t size, uint32_t val) "ioapic mem write addr 0x%"PRIx8" regsel: 0x%"PRIx8" size 0x%"PRIx8" val 0x%"PRIx32
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ioapic_set_irq(int vector, int level) "vector: %d level: %d"
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# hw/intc/slavio_intctl.c
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slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = 0x%x"
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@ -135,6 +135,8 @@ static Property vhost_user_scsi_properties[] = {
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DEFINE_PROP_CHR("chardev", VirtIOSCSICommon, conf.chardev),
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DEFINE_PROP_UINT32("boot_tpgt", VirtIOSCSICommon, conf.boot_tpgt, 0),
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DEFINE_PROP_UINT32("num_queues", VirtIOSCSICommon, conf.num_queues, 1),
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DEFINE_PROP_UINT32("virtqueue_size", VirtIOSCSICommon, conf.virtqueue_size,
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128),
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DEFINE_PROP_UINT32("max_sectors", VirtIOSCSICommon, conf.max_sectors,
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0xFFFF),
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DEFINE_PROP_UINT32("cmd_per_lun", VirtIOSCSICommon, conf.cmd_per_lun, 128),
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@ -7,7 +7,7 @@
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typedef QemuMutex QemuRecMutex;
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#define qemu_rec_mutex_destroy qemu_mutex_destroy
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#define qemu_rec_mutex_lock qemu_mutex_lock
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#define qemu_rec_mutex_try_lock qemu_mutex_try_lock
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#define qemu_rec_mutex_trylock qemu_mutex_trylock
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#define qemu_rec_mutex_unlock qemu_mutex_unlock
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struct QemuMutex {
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@ -347,7 +347,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.feat_names = {
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"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
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"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
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NULL, NULL, NULL, NULL,
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NULL, "kvm-pv-tlb-flush", NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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@ -91,7 +91,7 @@ bool stat64_min_slow(Stat64 *s, uint64_t value)
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low = atomic_read(&s->low);
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orig = ((uint64_t)high << 32) | low;
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if (orig < value) {
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if (value < orig) {
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/* We have to set low before high, just like stat64_min reads
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* high before low. The value may become higher temporarily, but
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* stat64_get does not notice (it takes the lock) and the only ill
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@ -120,7 +120,7 @@ bool stat64_max_slow(Stat64 *s, uint64_t value)
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low = atomic_read(&s->low);
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orig = ((uint64_t)high << 32) | low;
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if (orig > value) {
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if (value > orig) {
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/* We have to set low before high, just like stat64_max reads
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* high before low. The value may become lower temporarily, but
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* stat64_get does not notice (it takes the lock) and the only ill
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