target/loongarch: Implement xvssrln xvssran
This patch includes:
- XVSSRLN.{B.H/H.W/W.D};
- XVSSRAN.{B.H/H.W/W.D};
- XVSSRLN.{BU.H/HU.W/WU.D};
- XVSSRAN.{BU.H/HU.W/WU.D};
- XVSSRLNI.{B.H/H.W/W.D/D.Q};
- XVSSRANI.{B.H/H.W/W.D/D.Q};
- XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-41-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
c50ce38a47
commit
6256c8caeb
@ -2136,6 +2136,36 @@ INSN_LASX(xvsrarni_h_w, vv_i)
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INSN_LASX(xvsrarni_w_d, vv_i)
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INSN_LASX(xvsrarni_d_q, vv_i)
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INSN_LASX(xvssrln_b_h, vvv)
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INSN_LASX(xvssrln_h_w, vvv)
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INSN_LASX(xvssrln_w_d, vvv)
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INSN_LASX(xvssran_b_h, vvv)
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INSN_LASX(xvssran_h_w, vvv)
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INSN_LASX(xvssran_w_d, vvv)
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INSN_LASX(xvssrln_bu_h, vvv)
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INSN_LASX(xvssrln_hu_w, vvv)
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INSN_LASX(xvssrln_wu_d, vvv)
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INSN_LASX(xvssran_bu_h, vvv)
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INSN_LASX(xvssran_hu_w, vvv)
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INSN_LASX(xvssran_wu_d, vvv)
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INSN_LASX(xvssrlni_b_h, vv_i)
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INSN_LASX(xvssrlni_h_w, vv_i)
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INSN_LASX(xvssrlni_w_d, vv_i)
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INSN_LASX(xvssrlni_d_q, vv_i)
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INSN_LASX(xvssrani_b_h, vv_i)
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INSN_LASX(xvssrani_h_w, vv_i)
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INSN_LASX(xvssrani_w_d, vv_i)
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INSN_LASX(xvssrani_d_q, vv_i)
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INSN_LASX(xvssrlni_bu_h, vv_i)
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INSN_LASX(xvssrlni_hu_w, vv_i)
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INSN_LASX(xvssrlni_wu_d, vv_i)
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INSN_LASX(xvssrlni_du_q, vv_i)
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INSN_LASX(xvssrani_bu_h, vv_i)
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INSN_LASX(xvssrani_hu_w, vv_i)
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INSN_LASX(xvssrani_wu_d, vv_i)
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INSN_LASX(xvssrani_du_q, vv_i)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -3837,6 +3837,18 @@ TRANS(vssrln_wu_d, LSX, gen_vvv, gen_helper_vssrln_wu_d)
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TRANS(vssran_bu_h, LSX, gen_vvv, gen_helper_vssran_bu_h)
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TRANS(vssran_hu_w, LSX, gen_vvv, gen_helper_vssran_hu_w)
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TRANS(vssran_wu_d, LSX, gen_vvv, gen_helper_vssran_wu_d)
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TRANS(xvssrln_b_h, LASX, gen_xxx, gen_helper_vssrln_b_h)
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TRANS(xvssrln_h_w, LASX, gen_xxx, gen_helper_vssrln_h_w)
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TRANS(xvssrln_w_d, LASX, gen_xxx, gen_helper_vssrln_w_d)
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TRANS(xvssran_b_h, LASX, gen_xxx, gen_helper_vssran_b_h)
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TRANS(xvssran_h_w, LASX, gen_xxx, gen_helper_vssran_h_w)
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TRANS(xvssran_w_d, LASX, gen_xxx, gen_helper_vssran_w_d)
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TRANS(xvssrln_bu_h, LASX, gen_xxx, gen_helper_vssrln_bu_h)
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TRANS(xvssrln_hu_w, LASX, gen_xxx, gen_helper_vssrln_hu_w)
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TRANS(xvssrln_wu_d, LASX, gen_xxx, gen_helper_vssrln_wu_d)
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TRANS(xvssran_bu_h, LASX, gen_xxx, gen_helper_vssran_bu_h)
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TRANS(xvssran_hu_w, LASX, gen_xxx, gen_helper_vssran_hu_w)
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TRANS(xvssran_wu_d, LASX, gen_xxx, gen_helper_vssran_wu_d)
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TRANS(vssrlni_b_h, LSX, gen_vv_i, gen_helper_vssrlni_b_h)
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TRANS(vssrlni_h_w, LSX, gen_vv_i, gen_helper_vssrlni_h_w)
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@ -3854,6 +3866,22 @@ TRANS(vssrani_bu_h, LSX, gen_vv_i, gen_helper_vssrani_bu_h)
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TRANS(vssrani_hu_w, LSX, gen_vv_i, gen_helper_vssrani_hu_w)
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TRANS(vssrani_wu_d, LSX, gen_vv_i, gen_helper_vssrani_wu_d)
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TRANS(vssrani_du_q, LSX, gen_vv_i, gen_helper_vssrani_du_q)
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TRANS(xvssrlni_b_h, LASX, gen_xx_i, gen_helper_vssrlni_b_h)
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TRANS(xvssrlni_h_w, LASX, gen_xx_i, gen_helper_vssrlni_h_w)
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TRANS(xvssrlni_w_d, LASX, gen_xx_i, gen_helper_vssrlni_w_d)
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TRANS(xvssrlni_d_q, LASX, gen_xx_i, gen_helper_vssrlni_d_q)
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TRANS(xvssrani_b_h, LASX, gen_xx_i, gen_helper_vssrani_b_h)
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TRANS(xvssrani_h_w, LASX, gen_xx_i, gen_helper_vssrani_h_w)
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TRANS(xvssrani_w_d, LASX, gen_xx_i, gen_helper_vssrani_w_d)
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TRANS(xvssrani_d_q, LASX, gen_xx_i, gen_helper_vssrani_d_q)
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TRANS(xvssrlni_bu_h, LASX, gen_xx_i, gen_helper_vssrlni_bu_h)
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TRANS(xvssrlni_hu_w, LASX, gen_xx_i, gen_helper_vssrlni_hu_w)
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TRANS(xvssrlni_wu_d, LASX, gen_xx_i, gen_helper_vssrlni_wu_d)
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TRANS(xvssrlni_du_q, LASX, gen_xx_i, gen_helper_vssrlni_du_q)
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TRANS(xvssrani_bu_h, LASX, gen_xx_i, gen_helper_vssrani_bu_h)
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TRANS(xvssrani_hu_w, LASX, gen_xx_i, gen_helper_vssrani_hu_w)
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TRANS(xvssrani_wu_d, LASX, gen_xx_i, gen_helper_vssrani_wu_d)
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TRANS(xvssrani_du_q, LASX, gen_xx_i, gen_helper_vssrani_du_q)
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TRANS(vssrlrn_b_h, LSX, gen_vvv, gen_helper_vssrlrn_b_h)
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TRANS(vssrlrn_h_w, LSX, gen_vvv, gen_helper_vssrlrn_h_w)
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@ -1710,6 +1710,36 @@ xvsrarni_h_w 0111 01110101 11001 ..... ..... ..... @vv_ui5
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xvsrarni_w_d 0111 01110101 1101 ...... ..... ..... @vv_ui6
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xvsrarni_d_q 0111 01110101 111 ....... ..... ..... @vv_ui7
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xvssrln_b_h 0111 01001111 11001 ..... ..... ..... @vvv
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xvssrln_h_w 0111 01001111 11010 ..... ..... ..... @vvv
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xvssrln_w_d 0111 01001111 11011 ..... ..... ..... @vvv
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xvssran_b_h 0111 01001111 11101 ..... ..... ..... @vvv
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xvssran_h_w 0111 01001111 11110 ..... ..... ..... @vvv
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xvssran_w_d 0111 01001111 11111 ..... ..... ..... @vvv
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xvssrln_bu_h 0111 01010000 01001 ..... ..... ..... @vvv
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xvssrln_hu_w 0111 01010000 01010 ..... ..... ..... @vvv
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xvssrln_wu_d 0111 01010000 01011 ..... ..... ..... @vvv
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xvssran_bu_h 0111 01010000 01101 ..... ..... ..... @vvv
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xvssran_hu_w 0111 01010000 01110 ..... ..... ..... @vvv
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xvssran_wu_d 0111 01010000 01111 ..... ..... ..... @vvv
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xvssrlni_b_h 0111 01110100 10000 1 .... ..... ..... @vv_ui4
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xvssrlni_h_w 0111 01110100 10001 ..... ..... ..... @vv_ui5
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xvssrlni_w_d 0111 01110100 1001 ...... ..... ..... @vv_ui6
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xvssrlni_d_q 0111 01110100 101 ....... ..... ..... @vv_ui7
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xvssrani_b_h 0111 01110110 00000 1 .... ..... ..... @vv_ui4
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xvssrani_h_w 0111 01110110 00001 ..... ..... ..... @vv_ui5
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xvssrani_w_d 0111 01110110 0001 ...... ..... ..... @vv_ui6
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xvssrani_d_q 0111 01110110 001 ....... ..... ..... @vv_ui7
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xvssrlni_bu_h 0111 01110100 11000 1 .... ..... ..... @vv_ui4
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xvssrlni_hu_w 0111 01110100 11001 ..... ..... ..... @vv_ui5
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xvssrlni_wu_d 0111 01110100 1101 ...... ..... ..... @vv_ui6
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xvssrlni_du_q 0111 01110100 111 ....... ..... ..... @vv_ui7
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xvssrani_bu_h 0111 01110110 01000 1 .... ..... ..... @vv_ui4
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xvssrani_hu_w 0111 01110110 01001 ..... ..... ..... @vv_ui5
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xvssrani_wu_d 0111 01110110 0101 ...... ..... ..... @vv_ui6
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xvssrani_du_q 0111 01110110 011 ....... ..... ..... @vv_ui7
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -1401,23 +1401,29 @@ SSRLNS(B, uint16_t, int16_t, uint8_t)
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SSRLNS(H, uint32_t, int32_t, uint16_t)
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SSRLNS(W, uint64_t, int64_t, uint32_t)
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#define VSSRLN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrlns_ ## E1(Vj->E2(i), (T)Vk->E2(i)% BIT, BIT/2 -1); \
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} \
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Vd->D(1) = 0; \
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#define VSSRLN(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_ssrlns_ ## E1(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT, \
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BIT / 2 - 1); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSSRLN(vssrln_b_h, 16, uint16_t, B, H)
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VSSRLN(vssrln_h_w, 32, uint32_t, H, W)
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VSSRLN(vssrln_w_d, 64, uint64_t, W, D)
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VSSRLN(vssrln_b_h, 16, B, H, UH)
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VSSRLN(vssrln_h_w, 32, H, W, UW)
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VSSRLN(vssrln_w_d, 64, W, D, UD)
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#define SSRANS(E, T1, T2) \
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static T1 do_ssrans_ ## E(T1 e2, int sa, int sh) \
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@ -1429,10 +1435,10 @@ static T1 do_ssrans_ ## E(T1 e2, int sa, int sh) \
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shft_res = e2 >> sa; \
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} \
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T2 mask; \
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mask = (1ll << sh) -1; \
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mask = (1ll << sh) - 1; \
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if (shft_res > mask) { \
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return mask; \
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} else if (shft_res < -(mask +1)) { \
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} else if (shft_res < -(mask + 1)) { \
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return ~mask; \
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} else { \
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return shft_res; \
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@ -1443,23 +1449,29 @@ SSRANS(B, int16_t, int8_t)
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SSRANS(H, int32_t, int16_t)
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SSRANS(W, int64_t, int32_t)
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#define VSSRAN(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrans_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2 -1); \
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} \
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Vd->D(1) = 0; \
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#define VSSRAN(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_ssrans_ ## E1(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT, \
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BIT / 2 - 1); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSSRAN(vssran_b_h, 16, uint16_t, B, H)
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VSSRAN(vssran_h_w, 32, uint32_t, H, W)
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VSSRAN(vssran_w_d, 64, uint64_t, W, D)
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VSSRAN(vssran_b_h, 16, B, H, UH)
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VSSRAN(vssran_h_w, 32, H, W, UW)
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VSSRAN(vssran_w_d, 64, W, D, UD)
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#define SSRLNU(E, T1, T2, T3) \
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static T1 do_ssrlnu_ ## E(T3 e2, int sa, int sh) \
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@ -1471,7 +1483,7 @@ static T1 do_ssrlnu_ ## E(T3 e2, int sa, int sh) \
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shft_res = (((T1)e2) >> sa); \
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} \
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T2 mask; \
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mask = (1ull << sh) -1; \
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mask = (1ull << sh) - 1; \
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if (shft_res > mask) { \
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return mask; \
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} else { \
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@ -1483,23 +1495,29 @@ SSRLNU(B, uint16_t, uint8_t, int16_t)
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SSRLNU(H, uint32_t, uint16_t, int32_t)
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SSRLNU(W, uint64_t, uint32_t, int64_t)
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#define VSSRLNU(NAME, BIT, T, E1, E2) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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\
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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Vd->E1(i) = do_ssrlnu_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2); \
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} \
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Vd->D(1) = 0; \
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#define VSSRLNU(NAME, BIT, E1, E2, E3) \
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void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
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{ \
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int i, j, ofs; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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ofs = LSX_LEN / BIT; \
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for (i = 0; i < oprsz / 16; i++) { \
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for (j = 0; j < ofs; j++) { \
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Vd->E1(j + ofs * 2 * i) = do_ssrlnu_ ## E1(Vj->E2(j + ofs * i), \
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Vk->E3(j + ofs * i) % BIT, \
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BIT / 2); \
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} \
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Vd->D(2 * i + 1) = 0; \
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} \
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}
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VSSRLNU(vssrln_bu_h, 16, uint16_t, B, H)
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VSSRLNU(vssrln_hu_w, 32, uint32_t, H, W)
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VSSRLNU(vssrln_wu_d, 64, uint64_t, W, D)
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VSSRLNU(vssrln_bu_h, 16, B, H, UH)
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VSSRLNU(vssrln_hu_w, 32, H, W, UW)
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VSSRLNU(vssrln_wu_d, 64, W, D, UD)
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#define SSRANU(E, T1, T2, T3) \
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static T1 do_ssranu_ ## E(T3 e2, int sa, int sh) \
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@ -1514,7 +1532,7 @@ static T1 do_ssranu_ ## E(T3 e2, int sa, int sh) \
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shft_res = 0; \
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} \
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T2 mask; \
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mask = (1ull << sh) -1; \
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mask = (1ull << sh) - 1; \
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if (shft_res > mask) { \
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return mask; \
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||||
} else { \
|
||||
@ -1526,64 +1544,89 @@ SSRANU(B, uint16_t, uint8_t, int16_t)
|
||||
SSRANU(H, uint32_t, uint16_t, int32_t)
|
||||
SSRANU(W, uint64_t, uint32_t, int64_t)
|
||||
|
||||
#define VSSRANU(NAME, BIT, T, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
Vd->E1(i) = do_ssranu_ ## E1(Vj->E2(i), (T)Vk->E2(i)%BIT, BIT/2); \
|
||||
} \
|
||||
Vd->D(1) = 0; \
|
||||
#define VSSRANU(NAME, BIT, E1, E2, E3) \
|
||||
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
VReg *Vk = (VReg *)vk; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
Vd->E1(j + ofs * 2 * i) = do_ssranu_ ## E1(Vj->E2(j + ofs * i), \
|
||||
Vk->E3(j + ofs * i) % BIT, \
|
||||
BIT / 2); \
|
||||
} \
|
||||
Vd->D(2 * i + 1) = 0; \
|
||||
} \
|
||||
}
|
||||
|
||||
VSSRANU(vssran_bu_h, 16, uint16_t, B, H)
|
||||
VSSRANU(vssran_hu_w, 32, uint32_t, H, W)
|
||||
VSSRANU(vssran_wu_d, 64, uint64_t, W, D)
|
||||
VSSRANU(vssran_bu_h, 16, B, H, UH)
|
||||
VSSRANU(vssran_hu_w, 32, H, W, UW)
|
||||
VSSRANU(vssran_wu_d, 64, W, D, UD)
|
||||
|
||||
#define VSSRLNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrlns_ ## E1(Vj->E2(i), imm, BIT/2 -1); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrlns_ ## E1(Vd->E2(i), imm, BIT/2 -1);\
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRLNI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrlns_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrlns_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
static void do_vssrlni_q(VReg *Vd, VReg *Vj,
|
||||
uint64_t imm, int idx, Int128 mask)
|
||||
{
|
||||
Int128 shft_res1, shft_res2;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(idx);
|
||||
shft_res2 = Vd->Q(idx);
|
||||
} else {
|
||||
shft_res1 = int128_urshift(Vj->Q(idx), imm);
|
||||
shft_res2 = int128_urshift(Vd->Q(idx), imm);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res1)) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(idx * 2) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res2)) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(vssrlni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask;
|
||||
int i;
|
||||
Int128 mask;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
shft_res1 = int128_urshift(Vj->Q(0), imm);
|
||||
shft_res2 = int128_urshift(Vd->Q(0), imm);
|
||||
}
|
||||
mask = int128_sub(int128_lshift(int128_one(), 63), int128_one());
|
||||
|
||||
if (int128_ult(mask, shft_res1)) {
|
||||
Vd->D(0) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res2)) {
|
||||
Vd->D(1) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrlni_q(Vd, Vj, imm, i, mask);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1591,98 +1634,111 @@ VSSRLNI(vssrlni_b_h, 16, B, H)
|
||||
VSSRLNI(vssrlni_h_w, 32, H, W)
|
||||
VSSRLNI(vssrlni_w_d, 64, W, D)
|
||||
|
||||
#define VSSRANI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrans_ ## E1(Vj->E2(i), imm, BIT/2 -1); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrans_ ## E1(Vd->E2(i), imm, BIT/2 -1); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRANI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrans_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrans_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2 - 1); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
static void do_vssrani_d_q(VReg *Vd, VReg *Vj,
|
||||
uint64_t imm, int idx, Int128 mask, Int128 min)
|
||||
{
|
||||
Int128 shft_res1, shft_res2;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(idx);
|
||||
shft_res2 = Vd->Q(idx);
|
||||
} else {
|
||||
shft_res1 = int128_rshift(Vj->Q(idx), imm);
|
||||
shft_res2 = int128_rshift(Vd->Q(idx), imm);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res1, mask)) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask);
|
||||
} else if (int128_lt(shft_res1, int128_neg(min))) {
|
||||
Vd->D(idx * 2) = int128_getlo(min);
|
||||
} else {
|
||||
Vd->D(idx * 2) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask)) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask);
|
||||
} else if (int128_lt(shft_res2, int128_neg(min))) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(min);
|
||||
} else {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(shft_res2);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(vssrani_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask, min;
|
||||
int i;
|
||||
Int128 mask, min;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
shft_res1 = int128_rshift(Vj->Q(0), imm);
|
||||
shft_res2 = int128_rshift(Vd->Q(0), imm);
|
||||
}
|
||||
mask = int128_sub(int128_lshift(int128_one(), 63), int128_one());
|
||||
min = int128_lshift(int128_one(), 63);
|
||||
|
||||
if (int128_gt(shft_res1, mask)) {
|
||||
Vd->D(0) = int128_getlo(mask);
|
||||
} else if (int128_lt(shft_res1, int128_neg(min))) {
|
||||
Vd->D(0) = int128_getlo(min);
|
||||
} else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_gt(shft_res2, mask)) {
|
||||
Vd->D(1) = int128_getlo(mask);
|
||||
} else if (int128_lt(shft_res2, int128_neg(min))) {
|
||||
Vd->D(1) = int128_getlo(min);
|
||||
} else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrani_d_q(Vd, Vj, imm, i, mask, min);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
VSSRANI(vssrani_b_h, 16, B, H)
|
||||
VSSRANI(vssrani_h_w, 32, H, W)
|
||||
VSSRANI(vssrani_w_d, 64, W, D)
|
||||
|
||||
#define VSSRLNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssrlnu_ ## E1(Vj->E2(i), imm, BIT/2); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssrlnu_ ## E1(Vd->E2(i), imm, BIT/2); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRLNUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssrlnu_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssrlnu_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
void HELPER(vssrlni_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask;
|
||||
int i;
|
||||
Int128 mask;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
shft_res1 = int128_urshift(Vj->Q(0), imm);
|
||||
shft_res2 = int128_urshift(Vd->Q(0), imm);
|
||||
}
|
||||
mask = int128_sub(int128_lshift(int128_one(), 64), int128_one());
|
||||
|
||||
if (int128_ult(mask, shft_res1)) {
|
||||
Vd->D(0) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res2)) {
|
||||
Vd->D(1) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrlni_q(Vd, Vj, imm, i, mask);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1690,55 +1746,73 @@ VSSRLNUI(vssrlni_bu_h, 16, B, H)
|
||||
VSSRLNUI(vssrlni_hu_w, 32, H, W)
|
||||
VSSRLNUI(vssrlni_wu_d, 64, W, D)
|
||||
|
||||
#define VSSRANUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i; \
|
||||
VReg temp; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
temp.E1(i) = do_ssranu_ ## E1(Vj->E2(i), imm, BIT/2); \
|
||||
temp.E1(i + LSX_LEN/BIT) = do_ssranu_ ## E1(Vd->E2(i), imm, BIT/2); \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
#define VSSRANUI(NAME, BIT, E1, E2) \
|
||||
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
|
||||
{ \
|
||||
int i, j, ofs; \
|
||||
VReg temp = {}; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
ofs = LSX_LEN / BIT; \
|
||||
for (i = 0; i < oprsz / 16; i++) { \
|
||||
for (j = 0; j < ofs; j++) { \
|
||||
temp.E1(j + ofs * 2 * i) = do_ssranu_ ## E1(Vj->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
temp.E1(j + ofs * (2 * i + 1)) = do_ssranu_ ## E1(Vd->E2(j + ofs * i), \
|
||||
imm, BIT / 2); \
|
||||
} \
|
||||
} \
|
||||
*Vd = temp; \
|
||||
}
|
||||
|
||||
static void do_vssrani_du_q(VReg *Vd, VReg *Vj,
|
||||
uint64_t imm, int idx, Int128 mask)
|
||||
{
|
||||
Int128 shft_res1, shft_res2;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(idx);
|
||||
shft_res2 = Vd->Q(idx);
|
||||
} else {
|
||||
shft_res1 = int128_rshift(Vj->Q(idx), imm);
|
||||
shft_res2 = int128_rshift(Vd->Q(idx), imm);
|
||||
}
|
||||
|
||||
if (int128_lt(Vj->Q(idx), int128_zero())) {
|
||||
shft_res1 = int128_zero();
|
||||
}
|
||||
|
||||
if (int128_lt(Vd->Q(idx), int128_zero())) {
|
||||
shft_res2 = int128_zero();
|
||||
}
|
||||
if (int128_ult(mask, shft_res1)) {
|
||||
Vd->D(idx * 2) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(idx * 2) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res2)) {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(idx * 2 + 1) = int128_getlo(shft_res2);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void HELPER(vssrani_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
|
||||
{
|
||||
Int128 shft_res1, shft_res2, mask;
|
||||
int i;
|
||||
Int128 mask;
|
||||
VReg *Vd = (VReg *)vd;
|
||||
VReg *Vj = (VReg *)vj;
|
||||
|
||||
if (imm == 0) {
|
||||
shft_res1 = Vj->Q(0);
|
||||
shft_res2 = Vd->Q(0);
|
||||
} else {
|
||||
shft_res1 = int128_rshift(Vj->Q(0), imm);
|
||||
shft_res2 = int128_rshift(Vd->Q(0), imm);
|
||||
}
|
||||
|
||||
if (int128_lt(Vj->Q(0), int128_zero())) {
|
||||
shft_res1 = int128_zero();
|
||||
}
|
||||
|
||||
if (int128_lt(Vd->Q(0), int128_zero())) {
|
||||
shft_res2 = int128_zero();
|
||||
}
|
||||
int oprsz = simd_oprsz(desc);
|
||||
|
||||
mask = int128_sub(int128_lshift(int128_one(), 64), int128_one());
|
||||
|
||||
if (int128_ult(mask, shft_res1)) {
|
||||
Vd->D(0) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(0) = int128_getlo(shft_res1);
|
||||
}
|
||||
|
||||
if (int128_ult(mask, shft_res2)) {
|
||||
Vd->D(1) = int128_getlo(mask);
|
||||
}else {
|
||||
Vd->D(1) = int128_getlo(shft_res2);
|
||||
for (i = 0; i < oprsz / 16; i++) {
|
||||
do_vssrani_du_q(Vd, Vj, imm, i, mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user