i386: Add the support for AMD EPYC 3rd generation processors
Adds the support for AMD 3rd generation processors. The model
display for the new processor will be EPYC-Milan.
Adds the following new feature bits on top of the feature bits from
the first and second generation EPYC models.
pcid : Process context identifiers support
ibrs : Indirect Branch Restricted Speculation
ssbd : Speculative Store Bypass Disable
erms : Enhanced REP MOVSB/STOSB support
fsrm : Fast Short REP MOVSB support
invpcid : Invalidate processor context ID
pku : Protection keys support
svme-addr-chk : SVM instructions address check for #GP handling
Depends on the following kernel commits:
14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization")
3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change")
4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding")
4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD")
9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86")
3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c")
830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept")
4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area")
c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors")
9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts")
30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts")
03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts")
c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)")
a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field")
fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code")
38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD")
37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c")
Signed-off-by: Babu Moger <babu.moger@amd.com>
Message-Id: <161290460478.11352.8933244555799318236.stgit@bmoger-ubuntu>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Babu Moger
Eduardo Habkost
parent
c79f01c945
commit
623972ceae
@ -1033,7 +1033,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"clzero", NULL, "xsaveerptr", NULL,
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NULL, NULL, NULL, NULL,
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NULL, "wbnoinvd", NULL, NULL,
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"ibpb", NULL, NULL, "amd-stibp",
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"ibpb", NULL, "ibrs", "amd-stibp",
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
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@ -1798,6 +1798,56 @@ static CPUCaches epyc_rome_cache_info = {
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},
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};
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static CPUCaches epyc_milan_cache_info = {
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.l1d_cache = &(CPUCacheInfo) {
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.type = DATA_CACHE,
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.level = 1,
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.size = 32 * KiB,
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.line_size = 64,
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.associativity = 8,
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.partitions = 1,
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.sets = 64,
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.lines_per_tag = 1,
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.self_init = 1,
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.no_invd_sharing = true,
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},
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.l1i_cache = &(CPUCacheInfo) {
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.type = INSTRUCTION_CACHE,
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.level = 1,
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.size = 32 * KiB,
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.line_size = 64,
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.associativity = 8,
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.partitions = 1,
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.sets = 64,
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.lines_per_tag = 1,
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.self_init = 1,
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.no_invd_sharing = true,
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},
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.l2_cache = &(CPUCacheInfo) {
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.type = UNIFIED_CACHE,
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.level = 2,
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.size = 512 * KiB,
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.line_size = 64,
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.associativity = 8,
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.partitions = 1,
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.sets = 1024,
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.lines_per_tag = 1,
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},
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.l3_cache = &(CPUCacheInfo) {
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.type = UNIFIED_CACHE,
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.level = 3,
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.size = 32 * MiB,
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.line_size = 64,
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.associativity = 16,
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.partitions = 1,
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.sets = 32768,
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.lines_per_tag = 1,
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.self_init = true,
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.inclusive = true,
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.complex_indexing = true,
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},
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};
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/* The following VMX features are not supported by KVM and are left out in the
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* CPU definitions:
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*
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@ -4130,6 +4180,61 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "AMD EPYC-Rome Processor",
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.cache_info = &epyc_rome_cache_info,
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},
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{
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.name = "EPYC-Milan",
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.level = 0xd,
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.vendor = CPUID_VENDOR_AMD,
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.family = 25,
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.model = 1,
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.stepping = 1,
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.features[FEAT_1_EDX] =
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CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
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CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
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CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
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CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
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CPUID_VME | CPUID_FP87,
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.features[FEAT_1_ECX] =
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CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
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CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
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CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
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CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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CPUID_EXT_PCID,
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
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CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
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CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
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CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
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CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
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CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
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.features[FEAT_8000_0008_EBX] =
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CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
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CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
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CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
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CPUID_8000_0008_EBX_AMD_SSBD,
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
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CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
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CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
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CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
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CPUID_7_0_EBX_INVPCID,
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.features[FEAT_7_0_ECX] =
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CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
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.features[FEAT_7_0_EDX] =
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CPUID_7_0_EDX_FSRM,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.features[FEAT_SVM] =
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CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
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.xlevel = 0x8000001E,
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.model_id = "AMD EPYC-Milan Processor",
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.cache_info = &epyc_milan_cache_info,
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},
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};
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/* KVM-specific features that are automatically added/removed
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@ -817,8 +817,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
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/* Indirect Branch Prediction Barrier */
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#define CPUID_8000_0008_EBX_IBPB (1U << 12)
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/* Indirect Branch Restricted Speculation */
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#define CPUID_8000_0008_EBX_IBRS (1U << 14)
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/* Single Thread Indirect Branch Predictors */
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#define CPUID_8000_0008_EBX_STIBP (1U << 15)
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/* Speculative Store Bypass Disable */
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#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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