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target/microblaze: Add the div-zero-exception property

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Add the div-zero-exception property to control if the core
traps divizions by zero.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2019-10-30 14:03:38 +01:00
parent 5143fdf36f
commit 622cc7305c
3 changed files with 8 additions and 2 deletions
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4
target/microblaze/cpu.c
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@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DOPB_BUS_EXC_MASK : 0) | PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ? (cpu->cfg.iopb_bus_exception ?
PVR2_IOPB_BUS_EXC_MASK : 0) | PVR2_IOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.div_zero_exception ?
PVR2_DIV_ZERO_EXC_MASK : 0) |
(cpu->cfg.illegal_opcode_exception ? (cpu->cfg.illegal_opcode_exception ?
PVR2_ILL_OPCODE_EXC_MASK : 0) | PVR2_ILL_OPCODE_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ? (cpu->cfg.opcode_0_illegal ?
@ -280,6 +282,8 @@ static Property mb_properties[] = {
cfg.iopb_bus_exception, false), cfg.iopb_bus_exception, false),
DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
cfg.illegal_opcode_exception, false), cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
cfg.div_zero_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false), cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),

1
target/microblaze/cpu.h
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@ -305,6 +305,7 @@ struct MicroBlazeCPU {
bool iopb_bus_exception; bool iopb_bus_exception;
bool illegal_opcode_exception; bool illegal_opcode_exception;
bool opcode_0_illegal; bool opcode_0_illegal;
bool div_zero_exception;
char *version; char *version;
uint8_t pvr; uint8_t pvr;
} cfg; } cfg;

5
target/microblaze/op_helper.c
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@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{ {
MicroBlazeCPU *cpu = env_archcpu(env);
if (b == 0) { if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ; env->sregs[SR_MSR] |= MSR_DZ;
if ((env->sregs[SR_MSR] & MSR_EE) if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO; env->sregs[SR_ESR] = ESR_EC_DIVZERO;
helper_raise_exception(env, EXCP_HW_EXCP); helper_raise_exception(env, EXCP_HW_EXCP);
} }