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hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

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At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-06-08 07:17:37 -07:00 committed by Alistair Francis
parent 8a88b9f54f
commit 621c1006d2
1 changed files with 3 additions and 1 deletions
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2
hw/riscv/sifive_gpio.c
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@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
actual_value = pull;
}
if (output_en) {
qemu_set_irq(s->output[i], actual_value);
}
/* Input value */
ival = input_en && actual_value;