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target-i386: fix 32-bit addresses in LEA

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This was found with test-i386.  The issue is that instructions
such as

    addr32 lea (%eax), %rax

did not perform a 32-bit extension, because the LEA translation
skipped the gen_lea_v_seg step.  That step does not just add
segments, it also takes care of extending from address size to
pointer size.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2016-10-12 09:23:39 +02:00
parent 03514ac25c
commit 620abfb004
1 changed files with 7 additions and 7 deletions
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10
target-i386/translate.c
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@ -457,14 +457,13 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,
#endif #endif
case MO_32: case MO_32:
/* 32 bit address */ /* 32 bit address */
if (ovr_seg < 0) { if (ovr_seg < 0 && s->addseg) {
if (s->addseg) {
ovr_seg = def_seg; ovr_seg = def_seg;
} else { }
if (ovr_seg < 0) {
tcg_gen_ext32u_tl(cpu_A0, a0); tcg_gen_ext32u_tl(cpu_A0, a0);
return; return;
} }
}
break; break;
case MO_16: case MO_16:
/* 16 bit address */ /* 16 bit address */
@ -5372,7 +5371,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{ {
AddressParts a = gen_lea_modrm_0(env, s, modrm); AddressParts a = gen_lea_modrm_0(env, s, modrm);
TCGv ea = gen_lea_modrm_1(a); TCGv ea = gen_lea_modrm_1(a);
gen_op_mov_reg_v(dflag, reg, ea); gen_lea_v_seg(s, s->aflag, ea, -1, -1);
gen_op_mov_reg_v(dflag, reg, cpu_A0);
} }
break; break;