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target/arm: Convert LDR/STR with 12-bit immediate to decodetree

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Convert the LDR and STR instructions which use a 12-bit immediate
offset to decodetree. We can reuse the existing LDR and STR
trans functions for these.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-06-19 11:20:22 +01:00
parent 60cd7ba9c5
commit 61edd8f878
2 changed files with 41 additions and 88 deletions
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25
target/arm/tcg/a64.decode
View File

@ -395,3 +395,28 @@ STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0
STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
# Load/store with an unsigned 12 bit immediate, which is scaled by the
# element size. The function gets the sz:imm and returns the scaled immediate.
%uimm_scaled 10:12 sz:3 !function=uimm_scaled
@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled
STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0
LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1
LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2
LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3
LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0
LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1
LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2
LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0
LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1
# PRFM
NOP 11 111 0 01 10 ------------ ----- -----
STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4

104
target/arm/tcg/translate-a64.c
View File

@ -46,6 +46,22 @@ enum a64_shift_type {
A64_SHIFT_TYPE_ROR = 3
};
/*
* Helpers for extracting complex instruction fields
*/
/*
* For load/store with an unsigned 12 bit immediate scaled by the element
* size. The input has the immediate field in bits [14:3] and the element
* size in [2:0].
*/
static int uimm_scaled(DisasContext *s, int x)
{
unsigned imm = x >> 3;
unsigned scale = extract32(x, 0, 3);
return imm << scale;
}
/*
* Include the generated decoders.
*/
@ -3234,91 +3250,6 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
}
}
/*
* Load/store (unsigned immediate)
*
* 31 30 29 27 26 25 24 23 22 21 10 9 5
* +----+-------+---+-----+-----+------------+-------+------+
* |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
* +----+-------+---+-----+-----+------------+-------+------+
*
* For non-vector:
* size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
* For vector:
* size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
* opc<0>: 0 -> store, 1 -> load
* Rn: base address register (inc SP)
* Rt: target register
*/
static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
int opc,
int size,
int rt,
bool is_vector)
{
int rn = extract32(insn, 5, 5);
unsigned int imm12 = extract32(insn, 10, 12);
unsigned int offset;
TCGv_i64 clean_addr, dirty_addr;
bool is_store;
bool is_signed = false;
bool is_extended = false;
MemOp memop;
if (is_vector) {
size |= (opc & 2) << 1;
if (size > 4) {
unallocated_encoding(s);
return;
}
is_store = !extract32(opc, 0, 1);
if (!fp_access_check(s)) {
return;
}
memop = finalize_memop_asimd(s, size);
} else {
if (size == 3 && opc == 2) {
/* PRFM - prefetch */
return;
}
if (opc == 3 && size > 1) {
unallocated_encoding(s);
return;
}
is_store = (opc == 0);
is_signed = !is_store && extract32(opc, 1, 1);
is_extended = (size < 3) && extract32(opc, 0, 1);
memop = finalize_memop(s, size + is_signed * MO_SIGN);
}
if (rn == 31) {
gen_check_sp_alignment(s);
}
dirty_addr = read_cpu_reg_sp(s, rn, 1);
offset = imm12 << size;
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
clean_addr = gen_mte_check1(s, dirty_addr, is_store, rn != 31, memop);
if (is_vector) {
if (is_store) {
do_fp_st(s, rt, clean_addr, memop);
} else {
do_fp_ld(s, rt, clean_addr, memop);
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
if (is_store) {
do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false);
} else {
do_gpr_ld(s, tcg_rt, clean_addr, memop,
is_extended, true, rt, iss_sf, false);
}
}
}
/* Atomic memory operations
*
* 31 30 27 26 24 22 21 16 15 12 10 5 0
@ -3618,9 +3549,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
return;
}
break;
case 1:
disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector);
return;
}
unallocated_encoding(s);
}