ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality.
New IRQ gate consists of n_in input qdev gpio lines and one output sysbus IRQ line. The output IRQ level is formed as OR between all gpio inputs. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Evgeny Voevodin
Peter Maydell
parent
8aca521512
commit
61558e7a75
@ -97,11 +97,11 @@ void exynos4210_write_secondary(ARMCPU *cpu,
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Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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unsigned long ram_size)
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{
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qemu_irq cpu_irq[4];
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int n;
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qemu_irq cpu_irq[EXYNOS4210_NCPUS];
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int i, n;
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Exynos4210State *s = g_new(Exynos4210State, 1);
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qemu_irq *irqp;
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qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS];
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qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
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unsigned long mem_size;
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DeviceState *dev;
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SysBusDevice *busdev;
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@ -128,16 +128,18 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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s->irq_table = exynos4210_init_irq(&s->irqs);
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/* IRQ Gate */
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dev = qdev_create(NULL, "exynos4210.irq_gate");
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qdev_init_nofail(dev);
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/* Get IRQ Gate input in gate_irq */
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for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
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gate_irq[n] = qdev_get_gpio_in(dev, n);
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}
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busdev = sysbus_from_qdev(dev);
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/* Connect IRQ Gate output to cpu_irq */
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, cpu_irq[n]);
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for (i = 0; i < EXYNOS4210_NCPUS; i++) {
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dev = qdev_create(NULL, "exynos4210.irq_gate");
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qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
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qdev_init_nofail(dev);
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/* Get IRQ Gate input in gate_irq */
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for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
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gate_irq[i][n] = qdev_get_gpio_in(dev, n);
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}
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busdev = sysbus_from_qdev(dev);
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/* Connect IRQ Gate output to cpu_irq */
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sysbus_connect_irq(busdev, 0, cpu_irq[i]);
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}
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/* Private memory region and Internal GIC */
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@ -147,7 +149,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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busdev = sysbus_from_qdev(dev);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, gate_irq[n * 2]);
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sysbus_connect_irq(busdev, n, gate_irq[n][0]);
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}
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for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
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s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
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@ -166,7 +168,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
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/* Map Distributer interface */
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sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n, gate_irq[n * 2 + 1]);
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sysbus_connect_irq(busdev, n, gate_irq[n][1]);
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}
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for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
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s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
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@ -56,7 +56,7 @@
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/*
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* exynos4210 IRQ subsystem stub definitions.
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*/
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#define EXYNOS4210_IRQ_GATE_NINPUTS 8
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#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
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#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64
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#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16
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@ -362,61 +362,64 @@ static void exynos4210_gic_register_types(void)
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type_init(exynos4210_gic_register_types)
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/*
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* IRQGate struct.
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* IRQ Gate represents OR gate between GICs to pass IRQ to PIC.
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/* IRQ OR Gate struct.
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*
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* This device models an OR gate. There are n_in input qdev gpio lines and one
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* output sysbus IRQ line. The output IRQ level is formed as OR between all
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* gpio inputs.
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*/
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typedef struct {
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SysBusDevice busdev;
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qemu_irq pic_irq[EXYNOS4210_NCPUS]; /* output IRQs to PICs */
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uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */
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uint32_t n_in; /* inputs amount */
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uint32_t *level; /* input levels */
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qemu_irq out; /* output IRQ */
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} Exynos4210IRQGateState;
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static Property exynos4210_irq_gate_properties[] = {
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DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_exynos4210_irq_gate = {
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.name = "exynos4210.irq_gate",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(gpio_level, Exynos4210IRQGateState,
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EXYNOS4210_IRQ_GATE_NINPUTS),
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VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, 0, n_in),
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VMSTATE_END_OF_LIST()
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}
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};
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/* Process a change in an external IRQ input. */
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/* Process a change in IRQ input. */
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static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
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{
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Exynos4210IRQGateState *s =
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(Exynos4210IRQGateState *)opaque;
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uint32_t odd, even;
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Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
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uint32_t i;
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if (irq & 1) {
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odd = irq;
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even = irq & ~1;
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} else {
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even = irq;
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odd = irq | 1;
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assert(irq < s->n_in);
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s->level[irq] = level;
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for (i = 0; i < s->n_in; i++) {
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if (s->level[i] >= 1) {
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qemu_irq_raise(s->out);
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return;
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}
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}
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assert(irq < EXYNOS4210_IRQ_GATE_NINPUTS);
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s->gpio_level[irq] = level;
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if (s->gpio_level[odd] >= 1 || s->gpio_level[even] >= 1) {
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qemu_irq_raise(s->pic_irq[even >> 1]);
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} else {
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qemu_irq_lower(s->pic_irq[even >> 1]);
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}
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qemu_irq_lower(s->out);
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return;
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}
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static void exynos4210_irq_gate_reset(DeviceState *d)
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{
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Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)d;
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Exynos4210IRQGateState *s =
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DO_UPCAST(Exynos4210IRQGateState, busdev.qdev, d);
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memset(&s->gpio_level, 0, sizeof(s->gpio_level));
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memset(s->level, 0, s->n_in * sizeof(*s->level));
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}
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/*
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@ -424,19 +427,15 @@ static void exynos4210_irq_gate_reset(DeviceState *d)
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*/
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static int exynos4210_irq_gate_init(SysBusDevice *dev)
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{
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unsigned int i;
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Exynos4210IRQGateState *s =
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FROM_SYSBUS(Exynos4210IRQGateState, dev);
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Exynos4210IRQGateState *s = FROM_SYSBUS(Exynos4210IRQGateState, dev);
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/* Allocate general purpose input signals and connect a handler to each of
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* them */
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qdev_init_gpio_in(&s->busdev.qdev, exynos4210_irq_gate_handler,
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EXYNOS4210_IRQ_GATE_NINPUTS);
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qdev_init_gpio_in(&s->busdev.qdev, exynos4210_irq_gate_handler, s->n_in);
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/* Connect SysBusDev irqs to device specific irqs */
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for (i = 0; i < EXYNOS4210_NCPUS; i++) {
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sysbus_init_irq(dev, &s->pic_irq[i]);
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}
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s->level = g_malloc0(s->n_in * sizeof(*s->level));
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sysbus_init_irq(dev, &s->out);
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return 0;
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}
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@ -449,6 +448,7 @@ static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
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k->init = exynos4210_irq_gate_init;
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dc->reset = exynos4210_irq_gate_reset;
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dc->vmsd = &vmstate_exynos4210_irq_gate;
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dc->props = exynos4210_irq_gate_properties;
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}
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static TypeInfo exynos4210_irq_gate_info = {
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