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ppc patch queue 2020-06-26

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Here's another pull request for qemu-5.1.  Not very much in this one,
 just a handful of assorted minor fixes and cleanups.
 
 I'm about to go on holiday for a couple of weeks, so this will be my
 last PR before the freeze, and maybe the last for 5.1 at all.  If
 there's some super important fix we need, Greg Kurz will handle it.
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200626' into staging

ppc patch queue 2020-06-26

Here's another pull request for qemu-5.1.  Not very much in this one,
just a handful of assorted minor fixes and cleanups.

I'm about to go on holiday for a couple of weeks, so this will be my
last PR before the freeze, and maybe the last for 5.1 at all.  If
there's some super important fix we need, Greg Kurz will handle it.

# gpg: Signature made Fri 26 Jun 2020 07:36:59 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.1-20200626:
  target/ppc: Remove TIDR from POWER10 processor
  ppc/pnv: Silence missing BMC warning with qtest
  spapr: Fix typos in comments and macro indentation
  spapr: Simplify some warning printing paths in spapr_caps.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-06-26 09:30:29 +01:00
commit 611ac63305
5 changed files with 16 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
hw/ppc/pnv.c
View File

@ -21,6 +21,7 @@
#include "qemu-common.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "sysemu/reset.h"
@ -587,9 +588,11 @@ static void pnv_reset(MachineState *machine)
bmc = pnv_bmc_find(&error_fatal);
if (!pnv->bmc) {
if (!bmc) {
warn_report("machine has no BMC device. Use '-device "
"ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
"to define one");
if (!qtest_enabled()) {
warn_report("machine has no BMC device. Use '-device "
"ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
"to define one");
}
} else {
pnv_bmc_set_pnor(bmc, pnv->pnor);
pnv->bmc = bmc;

28
hw/ppc/spapr_caps.c
View File

@ -248,23 +248,18 @@ SpaprCapPossible cap_cfpc_possible = {
static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val,
Error **errp)
{
Error *local_err = NULL;
uint8_t kvm_val = kvmppc_get_cap_safe_cache();
if (tcg_enabled() && val) {
/* TCG only supports broken, allow other values and print a warning */
error_setg(&local_err,
"TCG doesn't support requested feature, cap-cfpc=%s",
cap_cfpc_possible.vals[val]);
warn_report("TCG doesn't support requested feature, cap-cfpc=%s",
cap_cfpc_possible.vals[val]);
} else if (kvm_enabled() && (val > kvm_val)) {
error_setg(errp,
"Requested safe cache capability level not supported by kvm,"
" try appending -machine cap-cfpc=%s",
cap_cfpc_possible.vals[kvm_val]);
}
if (local_err != NULL)
warn_report_err(local_err);
}
SpaprCapPossible cap_sbbc_possible = {
@ -277,23 +272,18 @@ SpaprCapPossible cap_sbbc_possible = {
static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val,
Error **errp)
{
Error *local_err = NULL;
uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check();
if (tcg_enabled() && val) {
/* TCG only supports broken, allow other values and print a warning */
error_setg(&local_err,
"TCG doesn't support requested feature, cap-sbbc=%s",
cap_sbbc_possible.vals[val]);
warn_report("TCG doesn't support requested feature, cap-sbbc=%s",
cap_sbbc_possible.vals[val]);
} else if (kvm_enabled() && (val > kvm_val)) {
error_setg(errp,
"Requested safe bounds check capability level not supported by kvm,"
" try appending -machine cap-sbbc=%s",
cap_sbbc_possible.vals[kvm_val]);
}
if (local_err != NULL)
warn_report_err(local_err);
}
SpaprCapPossible cap_ibs_possible = {
@ -309,24 +299,18 @@ SpaprCapPossible cap_ibs_possible = {
static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr,
uint8_t val, Error **errp)
{
Error *local_err = NULL;
uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
if (tcg_enabled() && val) {
/* TCG only supports broken, allow other values and print a warning */
error_setg(&local_err,
"TCG doesn't support requested feature, cap-ibs=%s",
cap_ibs_possible.vals[val]);
warn_report("TCG doesn't support requested feature, cap-ibs=%s",
cap_ibs_possible.vals[val]);
} else if (kvm_enabled() && (val > kvm_val)) {
error_setg(errp,
"Requested safe indirect branch capability level not supported by kvm,"
" try appending -machine cap-ibs=%s",
cap_ibs_possible.vals[kvm_val]);
}
if (local_err != NULL) {
warn_report_err(local_err);
}
}
#define VALUE_DESC_TRISTATE " (broken, workaround, fixed)"

6
hw/ppc/spapr_vio.c
View File

@ -420,7 +420,7 @@ static void spapr_vio_busdev_reset(DeviceState *qdev)
}
/*
* The register property of a VIO device is defined in livirt using
* The register property of a VIO device is defined in libvirt using
* 0x1000 as a base register number plus a 0x1000 increment. For the
* VIO tty device, the base number is changed to 0x30000000. QEMU uses
* a base register number of 0x71000000 and then a simple increment.
@ -450,7 +450,7 @@ static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg)
} else if (reg >= 0x30000000) {
/*
* VIO tty devices register values, when allocated by livirt,
* VIO tty devices register values, when allocated by libvirt,
* are mapped in range [0xf0 - 0xff], gives us a maximum of 16
* vtys.
*/
@ -459,7 +459,7 @@ static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg)
} else {
/*
* Other VIO devices register values, when allocated by
* livirt, should be mapped in range [0x00 - 0xef]. Conflicts
* libvirt, should be mapped in range [0x00 - 0xef]. Conflicts
* will be detected when IRQ is claimed.
*/
irq = (reg >> 12) & 0xff;

2
include/hw/ppc/xive_regs.h
View File

@ -71,7 +71,7 @@
* QW word 2 contains the valid bit at the top and other fields
* depending on the QW.
*/
#define TM_WORD2 0x8
#define TM_WORD2 0x8
#define TM_QW0W2_VU PPC_BIT32(0)
#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
#define TM_QW1W2_VO PPC_BIT32(0)

5
target/ppc/translate_init.inc.c
View File

@ -9086,11 +9086,6 @@ static void init_proc_POWER10(CPUPPCState *env)
gen_spr_power8_rpr(env);
gen_spr_power9_mmu(env);
/* POWER9 Specific registers */
spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
spr_read_generic, spr_write_generic,
KVM_REG_PPC_TIDR, 0);
/* FIXME: Filter fields properly based on privilege level */
spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
spr_read_generic, spr_write_generic,