Remove an unused field and fix some non-code typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -62,7 +62,6 @@ struct menelaus_s {
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int sec_offset;
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int alm_sec;
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int next_comp;
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struct tm *(*gettime)(const time_t *timep, struct tm *result);
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} rtc;
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qemu_irq handler[3];
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qemu_irq *in;
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@ -737,7 +737,7 @@ void do_interrupt(CPUARMState *env)
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new_mode = ARM_CPU_MODE_SVC;
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addr = 0x08;
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mask = CPSR_I;
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/* The PC already points to the next instructon. */
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/* The PC already points to the next instruction. */
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offset = 0;
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break;
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case EXCP_BKPT:
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@ -870,7 +870,7 @@ static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
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type = (desc & 3);
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domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
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if (type == 0) {
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/* Secton translation fault. */
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/* Section translation fault. */
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code = 5;
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goto do_fault;
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}
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@ -961,7 +961,7 @@ static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
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desc = ldl_phys(table);
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type = (desc & 3);
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if (type == 0) {
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/* Secton translation fault. */
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/* Section translation fault. */
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code = 5;
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domain = 0;
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goto do_fault;
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@ -6887,7 +6887,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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if (!(arm_feature(env, ARM_FEATURE_THUMB2)
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|| arm_feature (env, ARM_FEATURE_M))) {
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/* Thumb-1 cores may need to tread bl and blx as a pair of
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/* Thumb-1 cores may need to treat bl and blx as a pair of
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16-bit instructions to get correct prefetch abort behavior. */
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insn = insn_hw1;
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if ((insn & (1 << 12)) == 0) {
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