mirror of https://gitlab.com/qemu-project/qemu
target/arm: implement DBGCLAIM registers
The architecture does not define any functionality for the CLAIM tag bits. So we will just keep the raw bits, as per spec. Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230120155929.32384-2-eiakovlev@linux.microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -495,6 +495,7 @@ typedef struct CPUArchState {
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uint64_t dbgbcr[16]; /* breakpoint control registers */
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uint64_t dbgbcr[16]; /* breakpoint control registers */
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uint64_t dbgwvr[16]; /* watchpoint value registers */
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uint64_t dbgwvr[16]; /* watchpoint value registers */
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uint64_t dbgwcr[16]; /* watchpoint control registers */
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uint64_t dbgwcr[16]; /* watchpoint control registers */
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uint64_t dbgclaim; /* DBGCLAIM bits */
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uint64_t mdscr_el1;
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uint64_t mdscr_el1;
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uint64_t oslsr_el1; /* OS Lock Status */
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uint64_t oslsr_el1; /* OS Lock Status */
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uint64_t osdlr_el1; /* OS DoubleLock status */
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uint64_t osdlr_el1; /* OS DoubleLock status */
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@ -632,6 +632,24 @@ static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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}
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}
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}
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static void dbgclaimset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.dbgclaim |= (value & 0xFF);
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}
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static uint64_t dbgclaimset_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/* CLAIM bits are RAO */
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return 0xFF;
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}
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static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.dbgclaim &= ~(value & 0xFF);
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}
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static const ARMCPRegInfo debug_cp_reginfo[] = {
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static const ARMCPRegInfo debug_cp_reginfo[] = {
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/*
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/*
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* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
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* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
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@ -715,6 +733,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tda,
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.access = PL1_RW, .accessfn = access_tda,
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.type = ARM_CP_NOP },
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.type = ARM_CP_NOP },
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/*
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* Dummy DBGCLAIM registers.
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* "The architecture does not define any functionality for the CLAIM tag bits.",
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* so we only keep the raw bits
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*/
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{ .name = "DBGCLAIMSET_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
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.type = ARM_CP_ALIAS,
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.access = PL1_RW, .accessfn = access_tda,
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.writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
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{ .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
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.access = PL1_RW, .accessfn = access_tda,
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.writefn = dbgclaimclr_write, .raw_writefn = raw_write,
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.fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
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};
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};
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static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
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static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
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