hw/intc: Remove loongarch_ipi.c
It was missed out in previous commit.
Fixes: b4a12dfc21 ("hw/intc/loongarch_ipi: Rename as loongson_ipi")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240605-loongson3-ipi-v3-1-ddd2c0e03fa3@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Jiaxun Yang
Philippe Mathieu-Daudé
parent
283720489f
commit
5f82fb2a3a
@ -1,347 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch ipi interrupt support
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/intc/loongarch_ipi.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h"
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#include "migration/vmstate.h"
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#include "target/loongarch/cpu.h"
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#include "trace.h"
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static MemTxResult loongarch_ipi_readl(void *opaque, hwaddr addr,
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uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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IPICore *s;
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LoongArchIPI *ipi = opaque;
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uint64_t ret = 0;
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int index = 0;
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s = &ipi->cpu[attrs.requester_id];
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addr &= 0xff;
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switch (addr) {
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case CORE_STATUS_OFF:
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ret = s->status;
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break;
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case CORE_EN_OFF:
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ret = s->en;
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break;
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case CORE_SET_OFF:
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ret = 0;
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break;
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case CORE_CLEAR_OFF:
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ret = 0;
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break;
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case CORE_BUF_20 ... CORE_BUF_38 + 4:
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index = (addr - CORE_BUF_20) >> 2;
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ret = s->buf[index];
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "invalid read: %x", (uint32_t)addr);
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break;
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}
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trace_loongarch_ipi_read(size, (uint64_t)addr, ret);
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*data = ret;
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return MEMTX_OK;
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}
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static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr,
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MemTxAttrs attrs)
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{
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int i, mask = 0, data = 0;
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/*
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* bit 27-30 is mask for byte writing,
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* if the mask is 0, we need not to do anything.
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*/
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if ((val >> 27) & 0xf) {
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data = address_space_ldl(env->address_space_iocsr, addr,
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attrs, NULL);
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for (i = 0; i < 4; i++) {
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/* get mask for byte writing */
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if (val & (0x1 << (27 + i))) {
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mask |= 0xff << (i * 8);
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}
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}
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}
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data &= mask;
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data |= (val >> 32) & ~mask;
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address_space_stl(env->address_space_iocsr, addr,
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data, attrs, NULL);
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}
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static int archid_cmp(const void *a, const void *b)
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{
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CPUArchId *archid_a = (CPUArchId *)a;
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CPUArchId *archid_b = (CPUArchId *)b;
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return archid_a->arch_id - archid_b->arch_id;
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}
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static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id)
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{
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CPUArchId apic_id, *found_cpu;
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apic_id.arch_id = id;
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found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
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ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
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archid_cmp);
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return found_cpu;
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}
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static CPUState *ipi_getcpu(int arch_id)
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{
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MachineState *machine = MACHINE(qdev_get_machine());
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CPUArchId *archid;
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archid = find_cpu_by_archid(machine, arch_id);
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if (archid) {
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return CPU(archid->cpu);
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}
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return NULL;
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}
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static MemTxResult mail_send(uint64_t val, MemTxAttrs attrs)
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{
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uint32_t cpuid;
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hwaddr addr;
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CPUState *cs;
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cpuid = extract32(val, 16, 10);
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cs = ipi_getcpu(cpuid);
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if (cs == NULL) {
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return MEMTX_DECODE_ERROR;
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}
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/* override requester_id */
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addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c);
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attrs.requester_id = cs->cpu_index;
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send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs);
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return MEMTX_OK;
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}
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static MemTxResult any_send(uint64_t val, MemTxAttrs attrs)
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{
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uint32_t cpuid;
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hwaddr addr;
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CPUState *cs;
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cpuid = extract32(val, 16, 10);
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cs = ipi_getcpu(cpuid);
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if (cs == NULL) {
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return MEMTX_DECODE_ERROR;
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}
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/* override requester_id */
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addr = val & 0xffff;
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attrs.requester_id = cs->cpu_index;
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send_ipi_data(&LOONGARCH_CPU(cs)->env, val, addr, attrs);
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return MEMTX_OK;
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}
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static MemTxResult loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
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unsigned size, MemTxAttrs attrs)
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{
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LoongArchIPI *ipi = opaque;
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IPICore *s;
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int index = 0;
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uint32_t cpuid;
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uint8_t vector;
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CPUState *cs;
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s = &ipi->cpu[attrs.requester_id];
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addr &= 0xff;
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trace_loongarch_ipi_write(size, (uint64_t)addr, val);
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switch (addr) {
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case CORE_STATUS_OFF:
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qemu_log_mask(LOG_GUEST_ERROR, "can not be written");
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break;
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case CORE_EN_OFF:
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s->en = val;
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break;
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case CORE_SET_OFF:
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s->status |= val;
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if (s->status != 0 && (s->status & s->en) != 0) {
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qemu_irq_raise(s->irq);
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}
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break;
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case CORE_CLEAR_OFF:
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s->status &= ~val;
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if (s->status == 0 && s->en != 0) {
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qemu_irq_lower(s->irq);
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}
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break;
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case CORE_BUF_20 ... CORE_BUF_38 + 4:
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index = (addr - CORE_BUF_20) >> 2;
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s->buf[index] = val;
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break;
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case IOCSR_IPI_SEND:
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cpuid = extract32(val, 16, 10);
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/* IPI status vector */
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vector = extract8(val, 0, 5);
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cs = ipi_getcpu(cpuid);
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if (cs == NULL) {
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return MEMTX_DECODE_ERROR;
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}
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/* override requester_id */
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attrs.requester_id = cs->cpu_index;
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loongarch_ipi_writel(ipi, CORE_SET_OFF, BIT(vector), 4, attrs);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
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break;
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps loongarch_ipi_ops = {
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.read_with_attrs = loongarch_ipi_readl,
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.write_with_attrs = loongarch_ipi_writel,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 4,
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.valid.max_access_size = 8,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* mail send and any send only support writeq */
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static MemTxResult loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
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unsigned size, MemTxAttrs attrs)
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{
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MemTxResult ret = MEMTX_OK;
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addr &= 0xfff;
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switch (addr) {
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case MAIL_SEND_OFFSET:
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ret = mail_send(val, attrs);
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break;
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case ANY_SEND_OFFSET:
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ret = any_send(val, attrs);
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break;
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default:
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break;
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}
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return ret;
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}
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static const MemoryRegionOps loongarch_ipi64_ops = {
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.write_with_attrs = loongarch_ipi_writeq,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void loongarch_ipi_realize(DeviceState *dev, Error **errp)
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{
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LoongArchIPI *s = LOONGARCH_IPI(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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int i;
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if (s->num_cpu == 0) {
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error_setg(errp, "num-cpu must be at least 1");
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return;
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}
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memory_region_init_io(&s->ipi_iocsr_mem, OBJECT(dev), &loongarch_ipi_ops,
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s, "loongarch_ipi_iocsr", 0x48);
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/* loongarch_ipi_iocsr performs re-entrant IO through ipi_send */
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s->ipi_iocsr_mem.disable_reentrancy_guard = true;
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sysbus_init_mmio(sbd, &s->ipi_iocsr_mem);
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memory_region_init_io(&s->ipi64_iocsr_mem, OBJECT(dev),
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&loongarch_ipi64_ops,
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s, "loongarch_ipi64_iocsr", 0x118);
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sysbus_init_mmio(sbd, &s->ipi64_iocsr_mem);
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s->cpu = g_new0(IPICore, s->num_cpu);
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if (s->cpu == NULL) {
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error_setg(errp, "Memory allocation for ExtIOICore faile");
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return;
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}
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for (i = 0; i < s->num_cpu; i++) {
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qdev_init_gpio_out(dev, &s->cpu[i].irq, 1);
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}
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}
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static const VMStateDescription vmstate_ipi_core = {
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.name = "ipi-single",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(status, IPICore),
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VMSTATE_UINT32(en, IPICore),
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VMSTATE_UINT32(set, IPICore),
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VMSTATE_UINT32(clear, IPICore),
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VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_loongarch_ipi = {
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.name = TYPE_LOONGARCH_IPI,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (const VMStateField[]) {
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VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchIPI, num_cpu,
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vmstate_ipi_core, IPICore),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property ipi_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", LoongArchIPI, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void loongarch_ipi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = loongarch_ipi_realize;
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device_class_set_props(dc, ipi_properties);
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dc->vmsd = &vmstate_loongarch_ipi;
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}
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static void loongarch_ipi_finalize(Object *obj)
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{
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LoongArchIPI *s = LOONGARCH_IPI(obj);
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g_free(s->cpu);
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}
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static const TypeInfo loongarch_ipi_info = {
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.name = TYPE_LOONGARCH_IPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LoongArchIPI),
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.class_init = loongarch_ipi_class_init,
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.instance_finalize = loongarch_ipi_finalize,
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};
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static void loongarch_ipi_register_types(void)
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{
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type_register_static(&loongarch_ipi_info);
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}
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type_init(loongarch_ipi_register_types)
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