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ETRAX: Add NMI support to the watchdog and the interrupt controller.

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* Add NMI and GURU exceptions to teh interrupt controller.
* Teach the watchdog timer to signal an NMI before reseting the chip.
* Add etraxfs.h to hold api for etrax device models.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4720 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl 2008-06-09 23:33:30 +00:00
parent 1b1a38b0aa
commit 5ef98b4742
4 changed files with 119 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
hw/etraxfs.c
View File

@ -30,16 +30,7 @@
#include "devices.h"
#include "boards.h"
#include "etraxfs_dma.h"
/* Init functions for different blocks. */
extern qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
target_phys_addr_t base);
void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
qemu_irq *irq, target_phys_addr_t base);
void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
target_phys_addr_t base);
#include "etraxfs.h"
#define FLASH_SIZE 0x2000000
#define INTMEM_SIZE (128 * 1024)
@ -62,7 +53,7 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
qemu_irq *pic;
struct etraxfs_pic *pic;
void *etraxfs_dmac;
struct etraxfs_dma_client *eth[2] = {NULL, NULL};
int kernel_size;
@ -110,13 +101,13 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
etraxfs_dmac = etraxfs_dmac_init(env, 0xb0000000, 10);
for (i = 0; i < 10; i++) {
/* On ETRAX, odd numbered channels are inputs. */
etraxfs_dmac_connect(etraxfs_dmac, i, pic + 7 + i, i & 1);
etraxfs_dmac_connect(etraxfs_dmac, i, pic->irq + 7 + i, i & 1);
}
/* Add the two ethernet blocks. */
eth[0] = etraxfs_eth_init(&nd_table[0], env, pic + 25, 0xb0034000);
eth[0] = etraxfs_eth_init(&nd_table[0], env, pic->irq + 25, 0xb0034000);
if (nb_nics > 1)
eth[1] = etraxfs_eth_init(&nd_table[1], env, pic + 26, 0xb0036000);
eth[1] = etraxfs_eth_init(&nd_table[1], env, pic->irq + 26, 0xb0036000);
/* The DMA Connector block is missing, hardwire things for now. */
etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
@ -127,12 +118,12 @@ void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
}
/* 2 timers. */
etraxfs_timer_init(env, pic + 0x1b, 0xb001e000);
etraxfs_timer_init(env, pic + 0x1b, 0xb005e000);
etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0xb001e000);
etraxfs_timer_init(env, pic->irq + 0x1b, pic->nmi + 1, 0xb005e000);
for (i = 0; i < 4; i++) {
if (serial_hds[i]) {
etraxfs_ser_init(env, pic + 0x14 + i,
etraxfs_ser_init(env, pic->irq + 0x14 + i,
serial_hds[i], 0xb0026000 + i * 0x2000);
}
}

42
hw/etraxfs.h Normal file
View File

@ -0,0 +1,42 @@
/*
* QEMU ETRAX System Emulator
*
* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "etraxfs_dma.h"
struct etraxfs_pic
{
qemu_irq *irq;
qemu_irq *nmi;
qemu_irq *guru;
void *internal;
};
struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base);
void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
target_phys_addr_t base);
void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
qemu_irq *irq, target_phys_addr_t base);
void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
target_phys_addr_t base);

53
hw/etraxfs_pic.c
View File

@ -24,6 +24,7 @@
#include <stdio.h>
#include "hw.h"
#include "etraxfs.h"
#define D(x)
@ -143,7 +144,7 @@ void irq_info(void)
{
}
static void etraxfs_pic_handler(void *opaque, int irq, int level)
static void irq_handler(void *opaque, int irq, int level)
{
struct fs_pic_state_t *fs = (void *)opaque;
CPUState *env = fs->env;
@ -187,22 +188,56 @@ static void etraxfs_pic_handler(void *opaque, int irq, int level)
}
}
qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
static void nmi_handler(void *opaque, int irq, int level)
{
struct fs_pic_state_t *fs = (void *)opaque;
CPUState *env = fs->env;
uint32_t mask;
mask = 1 << irq;
if (level)
fs->r_nmi |= mask;
else
fs->r_nmi &= ~mask;
if (fs->r_nmi)
cpu_interrupt(env, CPU_INTERRUPT_NMI);
else
cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
}
static void guru_handler(void *opaque, int irq, int level)
{
struct fs_pic_state_t *fs = (void *)opaque;
CPUState *env = fs->env;
cpu_abort(env, "%s unsupported exception\n", __func__);
}
struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
{
struct fs_pic_state_t *fs;
qemu_irq *pic;
struct fs_pic_state_t *fs = NULL;
struct etraxfs_pic *pic = NULL;
int intr_vect_regs;
fs = qemu_mallocz(sizeof *fs);
if (!fs)
return NULL;
fs->env = env;
pic = qemu_mallocz(sizeof *pic);
pic->internal = fs = qemu_mallocz(sizeof *fs);
if (!fs || !pic)
goto err;
pic = qemu_allocate_irqs(etraxfs_pic_handler, fs, 30);
fs->env = env;
pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
pic->nmi = qemu_allocate_irqs(nmi_handler, fs, 2);
pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
cpu_register_physical_memory(base, 0x14, intr_vect_regs);
fs->base = base;
return pic;
err:
free(pic);
free(fs);
return NULL;
}

29
hw/etraxfs_timer.c
View File

@ -46,6 +46,7 @@
struct fs_timer_t {
CPUState *env;
qemu_irq *irq;
qemu_irq *nmi;
target_phys_addr_t base;
QEMUBH *bh_t0;
@ -56,6 +57,8 @@ struct fs_timer_t {
ptimer_state *ptimer_wd;
struct timeval last;
int wd_hits;
/* Control registers. */
uint32_t rw_tmr0_div;
uint32_t r_tmr0_data;
@ -129,6 +132,7 @@ static void update_ctrl(struct fs_timer_t *t, int tnum)
unsigned int freq_hz;
unsigned int div;
uint32_t ctrl;
ptimer_state *timer;
if (tnum == 0) {
@ -163,8 +167,8 @@ static void update_ctrl(struct fs_timer_t *t, int tnum)
D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
div = div * TIMER_SLOWDOWN;
div >>= 15;
freq_hz >>= 15;
div >>= 10;
freq_hz >>= 10;
ptimer_set_freq(timer, freq_hz);
ptimer_set_limit(timer, div, 0);
@ -216,7 +220,18 @@ static void timer1_hit(void *opaque)
static void watchdog_hit(void *opaque)
{
qemu_system_reset_request();
struct fs_timer_t *t = opaque;
if (t->wd_hits == 0) {
/* real hw gives a single tick before reseting but we are
a bit friendlier to compensate for our slower execution. */
ptimer_set_count(t->ptimer_wd, 10);
ptimer_run(t->ptimer_wd, 1);
qemu_irq_raise(t->nmi[0]);
}
else
qemu_system_reset_request();
t->wd_hits++;
}
static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
@ -237,6 +252,11 @@ static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
wd_en, new_key, wd_key, new_cmd, wd_cnt));
if (t->wd_hits)
qemu_irq_lower(t->nmi[0]);
t->wd_hits = 0;
ptimer_set_freq(t->ptimer_wd, 760);
if (wd_cnt == 0)
wd_cnt = 256;
@ -320,7 +340,7 @@ static void etraxfs_timer_reset(void *opaque)
qemu_irq_lower(t->irq[0]);
}
void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
target_phys_addr_t base)
{
static struct fs_timer_t *t;
@ -337,6 +357,7 @@ void etraxfs_timer_init(CPUState *env, qemu_irq *irqs,
t->ptimer_t1 = ptimer_init(t->bh_t1);
t->ptimer_wd = ptimer_init(t->bh_wd);
t->irq = irqs;
t->nmi = nmi;
t->env = env;
t->base = base;