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hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-07-09 13:38:39 +10:00
parent 24bfb98d06
commit 5ee257649f
2 changed files with 4 additions and 0 deletions
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3
hw/riscv/opentitan.c
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@ -58,6 +58,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
[IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
};
static void opentitan_board_init(MachineState *machine)
@ -217,6 +218,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
create_unimplemented_device("riscv.lowrisc.ibex.otbn",
memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
create_unimplemented_device("riscv.lowrisc.ibex.peri",
memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
}
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

1
include/hw/riscv/opentitan.h
View File

@ -81,6 +81,7 @@ enum {
IBEX_DEV_ALERT_HANDLER,
IBEX_DEV_NMI_GEN,
IBEX_DEV_OTBN,
IBEX_DEV_PERI,
};
enum {