target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0
Implement debug registers DBGVCR, OSDLR_EL1 and MDCCSR_EL0 (as dummy or limited-functionality). 32 bit Linux kernels will access these at startup so they are required for breakpoints and watchpoints to be supported. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2250,10 +2250,29 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
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.resetvalue = 0 },
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/* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
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* We don't implement the configurable EL0 access.
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*/
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{ .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
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.type = ARM_CP_NO_MIGRATE,
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.access = PL1_R,
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.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
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.resetfn = arm_cp_reset_ignore },
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/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
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{ .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
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.access = PL1_W, .type = ARM_CP_NOP },
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/* Dummy OSDLR_EL1: 32-bit Linux will read this */
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{ .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
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.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
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.access = PL1_RW, .type = ARM_CP_NOP },
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/* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
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* implement vector catch debug events yet.
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*/
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{ .name = "DBGVCR",
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.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_NOP },
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REGINFO_SENTINEL
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};
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