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disas/riscv: enable lpad disassembly

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Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-9-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Deepak Gupta 2024-10-08 15:49:58 -07:00 committed by Alistair Francis
parent 966f3a3895
commit 5e761bd613
2 changed files with 19 additions and 1 deletions
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18
disas/riscv.c
View File

@ -976,6 +976,7 @@ typedef enum {
rv_op_amocas_h = 945, rv_op_amocas_h = 945,
rv_op_wrs_sto = 946, rv_op_wrs_sto = 946,
rv_op_wrs_nto = 947, rv_op_wrs_nto = 947,
rv_op_lpad = 948,
} rv_op; } rv_op;
/* register names */ /* register names */
@ -2236,6 +2237,7 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
{ "lpad", rv_codec_lp, rv_fmt_imm, NULL, 0, 0, 0 },
}; };
/* CSR names */ /* CSR names */
@ -2929,7 +2931,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 7: op = rv_op_andi; break; case 7: op = rv_op_andi; break;
} }
break; break;
case 5: op = rv_op_auipc; break; case 5:
op = rv_op_auipc;
if (dec->cfg->ext_zicfilp &&
(((inst >> 7) & 0b11111) == 0b00000)) {
op = rv_op_lpad;
}
break;
case 6: case 6:
switch ((inst >> 12) & 0b111) { switch ((inst >> 12) & 0b111) {
case 0: op = rv_op_addiw; break; case 0: op = rv_op_addiw; break;
@ -4488,6 +4496,11 @@ static uint32_t operand_tbl_index(rv_inst inst)
return ((inst << 54) >> 56); return ((inst << 54) >> 56);
} }
static uint32_t operand_lpl(rv_inst inst)
{
return inst >> 12;
}
/* decode operands */ /* decode operands */
static void decode_inst_operands(rv_decode *dec, rv_isa isa) static void decode_inst_operands(rv_decode *dec, rv_isa isa)
@ -4875,6 +4888,9 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = sextract32(operand_rs2(inst), 0, 5); dec->imm = sextract32(operand_rs2(inst), 0, 5);
dec->imm1 = operand_imm2(inst); dec->imm1 = operand_imm2(inst);
break; break;
case rv_codec_lp:
dec->imm = operand_lpl(inst);
break;
}; };
} }

2
disas/riscv.h
View File

@ -166,6 +166,7 @@ typedef enum {
rv_codec_r2_immhl, rv_codec_r2_immhl,
rv_codec_r2_imm2_imm5, rv_codec_r2_imm2_imm5,
rv_codec_fli, rv_codec_fli,
rv_codec_lp,
} rv_codec; } rv_codec;
/* structures */ /* structures */
@ -228,6 +229,7 @@ enum {
#define rv_fmt_rs1_rs2 "O\t1,2" #define rv_fmt_rs1_rs2 "O\t1,2"
#define rv_fmt_rd_imm "O\t0,i" #define rv_fmt_rd_imm "O\t0,i"
#define rv_fmt_rd_uimm "O\t0,Ui" #define rv_fmt_rd_uimm "O\t0,Ui"
#define rv_fmt_imm "O\ti"
#define rv_fmt_rd_offset "O\t0,o" #define rv_fmt_rd_offset "O\t0,o"
#define rv_fmt_rd_uoffset "O\t0,Uo" #define rv_fmt_rd_uoffset "O\t0,Uo"
#define rv_fmt_rd_rs1_rs2 "O\t0,1,2" #define rv_fmt_rd_rs1_rs2 "O\t0,1,2"