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Merge remote-tracking branch 'mst/tags/for_anthony' into staging

Browse Source 
* mst/tags/for_anthony:
  msi/msix: added API to set MSI message address and data
  pci: Add INTx routing notifier
  pci: Add pci_device_route_intx_to_irq
  pci: Unregister BARs before device exit
  pci: convert PCIUnregisterFunc to void
  msix: Switch msix_uninit to return void
  msix: Allow full specification of MSIX layout
  msix: Split PBA into it's own MemoryRegion
  msix: Note endian TODO item
  msix: Move msix_mmio_read
  virtio: Convert to msix_init_exclusive_bar() interface
  ivshmem: Convert to msix_init_exclusive_bar() interface
  msix: Add simple BAR allocation MSIX setup functions
  msix: fix PCIDevice naming inconsistency
  msix: drop unused msix_bar_size, require valid bar_size
This commit is contained in:
Anthony Liguori 2012-07-30 10:00:48 -05:00
commit 5e3bc7144e
33 changed files with 338 additions and 249 deletions
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3
hw/ac97.c
View File

@ -1319,13 +1319,12 @@ static int ac97_initfn (PCIDevice *dev)
return 0;
}
static int ac97_exitfn (PCIDevice *dev)
static void ac97_exitfn (PCIDevice *dev)
{
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
memory_region_destroy (&s->io_nam);
memory_region_destroy (&s->io_nabm);
return 0;
}
int ac97_init (PCIBus *bus)

3
hw/e1000.c
View File

@ -1192,7 +1192,7 @@ e1000_cleanup(VLANClientState *nc)
s->nic = NULL;
}
static int
static void
pci_e1000_uninit(PCIDevice *dev)
{
E1000State *d = DO_UPCAST(E1000State, dev, dev);
@ -1202,7 +1202,6 @@ pci_e1000_uninit(PCIDevice *dev)
memory_region_destroy(&d->mmio);
memory_region_destroy(&d->io);
qemu_del_vlan_client(&d->nic->nc);
return 0;
}
static NetClientInfo net_e1000_info = {

3
hw/eepro100.c
View File

@ -1838,7 +1838,7 @@ static void nic_cleanup(VLANClientState *nc)
s->nic = NULL;
}
static int pci_nic_uninit(PCIDevice *pci_dev)
static void pci_nic_uninit(PCIDevice *pci_dev)
{
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
@ -1848,7 +1848,6 @@ static int pci_nic_uninit(PCIDevice *pci_dev)
vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
eeprom93xx_free(&pci_dev->qdev, s->eeprom);
qemu_del_vlan_client(&s->nic->nc);
return 0;
}
static NetClientInfo net_eepro100_info = {

3
hw/es1370.c
View File

@ -1018,12 +1018,11 @@ static int es1370_initfn (PCIDevice *dev)
return 0;
}
static int es1370_exitfn (PCIDevice *dev)
static void es1370_exitfn (PCIDevice *dev)
{
ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
memory_region_destroy (&s->io);
return 0;
}
int es1370_init (PCIBus *bus)

4
hw/esp.c
View File

@ -1153,13 +1153,11 @@ static int esp_pci_scsi_init(PCIDevice *dev)
return 0;
}
static int esp_pci_scsi_uninit(PCIDevice *d)
static void esp_pci_scsi_uninit(PCIDevice *d)
{
PCIESPState *pci = DO_UPCAST(PCIESPState, dev, d);
memory_region_destroy(&pci->io);
return 0;
}
static void esp_pci_class_init(ObjectClass *klass, void *data)

4
hw/ide/cmd646.c
View File

@ -295,7 +295,7 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
return 0;
}
static int pci_cmd646_ide_exitfn(PCIDevice *dev)
static void pci_cmd646_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
unsigned i;
@ -309,8 +309,6 @@ static int pci_cmd646_ide_exitfn(PCIDevice *dev)
memory_region_destroy(&d->cmd646_bar[i].data);
}
memory_region_destroy(&d->bmdma_bar);
return 0;
}
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,

4
hw/ide/ich.c
View File

@ -132,15 +132,13 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
return 0;
}
static int pci_ich9_uninit(PCIDevice *dev)
static void pci_ich9_uninit(PCIDevice *dev)
{
struct AHCIPCIState *d;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
msi_uninit(dev);
ahci_uninit(&d->ahci);
return 0;
}
static void ich_ahci_class_init(ObjectClass *klass, void *data)

4
hw/ide/piix.c
View File

@ -201,7 +201,7 @@ PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
return dev;
}
static int pci_piix_ide_exitfn(PCIDevice *dev)
static void pci_piix_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
unsigned i;
@ -213,8 +213,6 @@ static int pci_piix_ide_exitfn(PCIDevice *dev)
memory_region_destroy(&d->bmdma[i].addr_ioport);
}
memory_region_destroy(&d->bmdma_bar);
return 0;
}
/* hd_table must contain 4 block drivers */

4
hw/ide/via.c
View File

@ -190,7 +190,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
return 0;
}
static int vt82c686b_ide_exitfn(PCIDevice *dev)
static void vt82c686b_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
unsigned i;
@ -202,8 +202,6 @@ static int vt82c686b_ide_exitfn(PCIDevice *dev)
memory_region_destroy(&d->bmdma[i].addr_ioport);
}
memory_region_destroy(&d->bmdma_bar);
return 0;
}
void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)

3
hw/intel-hda.c
View File

@ -1149,13 +1149,12 @@ static int intel_hda_init(PCIDevice *pci)
return 0;
}
static int intel_hda_exit(PCIDevice *pci)
static void intel_hda_exit(PCIDevice *pci)
{
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
msi_uninit(&d->pci);
memory_region_destroy(&d->mmio);
return 0;
}
static int intel_hda_post_load(void *opaque, int version)

8
hw/ioh3420.c
View File

@ -96,7 +96,6 @@ static int ioh3420_initfn(PCIDevice *d)
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc;
int tmp;
rc = pci_bridge_initfn(d);
if (rc < 0) {
@ -144,12 +143,11 @@ err_pcie_cap:
err_msi:
msi_uninit(d);
err_bridge:
tmp = pci_bridge_exitfn(d);
assert(!tmp);
pci_bridge_exitfn(d);
return rc;
}
static int ioh3420_exitfn(PCIDevice *d)
static void ioh3420_exitfn(PCIDevice *d)
{
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
@ -159,7 +157,7 @@ static int ioh3420_exitfn(PCIDevice *d)
pcie_chassis_del_slot(s);
pcie_cap_exit(d);
msi_uninit(d);
return pci_bridge_exitfn(d);
pci_bridge_exitfn(d);
}
PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,

14
hw/ivshmem.c
View File

@ -70,7 +70,6 @@ typedef struct IVShmemState {
*/
MemoryRegion bar;
MemoryRegion ivshmem;
MemoryRegion msix_bar;
uint64_t ivshmem_size; /* size of shared memory region */
int shm_fd; /* shared memory file descriptor */
@ -574,16 +573,13 @@ static uint64_t ivshmem_get_size(IVShmemState * s) {
static void ivshmem_setup_msi(IVShmemState * s)
{
memory_region_init(&s->msix_bar, "ivshmem-msix", 4096);
if (!msix_init(&s->dev, s->vectors, &s->msix_bar, 1, 0)) {
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&s->msix_bar);
IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
} else {
if (msix_init_exclusive_bar(&s->dev, s->vectors, 1)) {
IVSHMEM_DPRINTF("msix initialization failed\n");
exit(1);
}
IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
/* allocate QEMU char devices for receiving interrupts */
s->eventfd_table = g_malloc0(s->vectors * sizeof(EventfdEntry));
@ -775,7 +771,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
return 0;
}
static int pci_ivshmem_uninit(PCIDevice *dev)
static void pci_ivshmem_uninit(PCIDevice *dev)
{
IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
@ -790,8 +786,6 @@ static int pci_ivshmem_uninit(PCIDevice *dev)
memory_region_destroy(&s->ivshmem);
memory_region_destroy(&s->bar);
unregister_savevm(&dev->qdev, "ivshmem", s);
return 0;
}
static Property ivshmem_properties[] = {

4
hw/lsi53c895a.c
View File

@ -2064,15 +2064,13 @@ static const VMStateDescription vmstate_lsi_scsi = {
}
};
static int lsi_scsi_uninit(PCIDevice *d)
static void lsi_scsi_uninit(PCIDevice *d)
{
LSIState *s = DO_UPCAST(LSIState, dev, d);
memory_region_destroy(&s->mmio_io);
memory_region_destroy(&s->ram_io);
memory_region_destroy(&s->io_io);
return 0;
}
static const struct SCSIBusInfo lsi_scsi_info = {

17
hw/msi.c
View File

@ -105,6 +105,23 @@ static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
}
/*
* Special API for POWER to configure the vectors through
* a side channel. Should never be used by devices.
*/
void msi_set_message(PCIDevice *dev, MSIMessage msg)
{
uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
if (msi64bit) {
pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
} else {
pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
}
pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
}
bool msi_enabled(const PCIDevice *dev)
{
return msi_present(dev) &&

1
hw/msi.h
View File

@ -31,6 +31,7 @@ struct MSIMessage {
extern bool msi_supported;
void msi_set_message(PCIDevice *dev, MSIMessage msg);
bool msi_enabled(const PCIDevice *dev);
int msi_init(struct PCIDevice *dev, uint8_t offset,
unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask);

292
hw/msix.c
View File

@ -27,17 +27,9 @@
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
* a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32
static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
{
uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
MSIMessage msg;
msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
@ -45,62 +37,17 @@ static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
return msg;
}
/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
* and fill MSI-X capability in the config space.
* Original bar size must be a power of 2 or 0.
* New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
unsigned bar_nr, unsigned bar_size)
/*
* Special API for POWER to configure the vectors through
* a side channel. Should never be used by devices.
*/
void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg)
{
int config_offset;
uint8_t *config;
uint32_t new_size;
uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
return -EINVAL;
if (bar_size > 0x80000000)
return -ENOSPC;
/* Add space for MSI-X structures */
if (!bar_size) {
new_size = MSIX_PAGE_SIZE;
} else if (bar_size < MSIX_PAGE_SIZE) {
bar_size = MSIX_PAGE_SIZE;
new_size = MSIX_PAGE_SIZE * 2;
} else {
new_size = bar_size * 2;
}
pdev->msix_bar_size = new_size;
config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
0, MSIX_CAP_LENGTH);
if (config_offset < 0)
return config_offset;
config = pdev->config + config_offset;
pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
/* Table on top of BAR */
pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
/* Pending bits on top of that */
pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
bar_nr);
pdev->msix_cap = config_offset;
/* Make flags bit writable. */
pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK;
pdev->msix_function_masked = true;
return 0;
}
static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIDevice *dev = opaque;
unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
void *page = dev->msix_table_page;
return pci_get_long(page + offset);
pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address);
pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data);
table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
}
static uint8_t msix_pending_mask(int vector)
@ -110,7 +57,7 @@ static uint8_t msix_pending_mask(int vector)
static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
return dev->msix_pba + vector / 8;
}
static int msix_is_pending(PCIDevice *dev, int vector)
@ -131,7 +78,7 @@ static void msix_clr_pending(PCIDevice *dev, int vector)
static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
{
unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
return fmask || dev->msix_table[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
}
static bool msix_is_masked(PCIDevice *dev, int vector)
@ -210,27 +157,30 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
}
}
static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
PCIDevice *dev = opaque;
unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
int vector = offset / PCI_MSIX_ENTRY_SIZE;
return pci_get_long(dev->msix_table + addr);
}
static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
PCIDevice *dev = opaque;
int vector = addr / PCI_MSIX_ENTRY_SIZE;
bool was_masked;
/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
if (vector >= dev->msix_entries_nr) {
return;
}
was_masked = msix_is_masked(dev, vector);
pci_set_long(dev->msix_table_page + offset, val);
pci_set_long(dev->msix_table + addr, val);
msix_handle_mask_update(dev, vector, was_masked);
}
static const MemoryRegionOps msix_mmio_ops = {
.read = msix_mmio_read,
.write = msix_mmio_write,
static const MemoryRegionOps msix_table_mmio_ops = {
.read = msix_table_mmio_read,
.write = msix_table_mmio_write,
/* TODO: MSIX should be LITTLE_ENDIAN. */
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
@ -238,17 +188,24 @@ static const MemoryRegionOps msix_mmio_ops = {
},
};
static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
uint8_t *config = d->config + d->msix_cap;
uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
/* TODO: for assigned devices, we'll want to make it possible to map
* pending bits separately in case they are in a separate bar. */
PCIDevice *dev = opaque;
memory_region_add_subregion(bar, offset, &d->msix_mmio);
return pci_get_long(dev->msix_pba + addr);
}
static const MemoryRegionOps msix_pba_mmio_ops = {
.read = msix_pba_mmio_read,
/* TODO: MSIX should be LITTLE_ENDIAN. */
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
{
int vector;
@ -258,52 +215,119 @@ static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
bool was_masked = msix_is_masked(dev, vector);
dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
msix_handle_mask_update(dev, vector, was_masked);
}
}
/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
* modified, it should be retrieved with msix_bar_size. */
/* Initialize the MSI-X structures */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
MemoryRegion *bar,
unsigned bar_nr, unsigned bar_size)
MemoryRegion *table_bar, uint8_t table_bar_nr,
unsigned table_offset, MemoryRegion *pba_bar,
uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos)
{
int ret;
int cap;
unsigned table_size, pba_size;
uint8_t *config;
/* Nothing to do if MSI is not supported by interrupt controller */
if (!msi_supported) {
return -ENOTSUP;
}
if (nentries > MSIX_MAX_ENTRIES)
if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
return -EINVAL;
}
dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
sizeof *dev->msix_entry_used);
table_size = nentries * PCI_MSIX_ENTRY_SIZE;
pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
/* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
if ((table_bar_nr == pba_bar_nr &&
ranges_overlap(table_offset, table_size, pba_offset, pba_size)) ||
table_offset + table_size > memory_region_size(table_bar) ||
pba_offset + pba_size > memory_region_size(pba_bar) ||
(table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
return -EINVAL;
}
cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH);
if (cap < 0) {
return cap;
}
dev->msix_cap = cap;
dev->cap_present |= QEMU_PCI_CAP_MSIX;
config = dev->config + cap;
pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
dev->msix_entries_nr = nentries;
dev->msix_function_masked = true;
pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr);
pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr);
/* Make flags bit writable. */
dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK;
dev->msix_table = g_malloc0(table_size);
dev->msix_pba = g_malloc0(pba_size);
dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
msix_mask_all(dev, nentries);
memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
"msix", MSIX_PAGE_SIZE);
memory_region_init_io(&dev->msix_table_mmio, &msix_table_mmio_ops, dev,
"msix-table", table_size);
memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
memory_region_init_io(&dev->msix_pba_mmio, &msix_pba_mmio_ops, dev,
"msix-pba", pba_size);
memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
dev->msix_entries_nr = nentries;
ret = msix_add_config(dev, nentries, bar_nr, bar_size);
if (ret)
goto err_config;
dev->cap_present |= QEMU_PCI_CAP_MSIX;
msix_mmio_setup(dev, bar);
return 0;
}
err_config:
dev->msix_entries_nr = 0;
memory_region_destroy(&dev->msix_mmio);
g_free(dev->msix_table_page);
dev->msix_table_page = NULL;
g_free(dev->msix_entry_used);
dev->msix_entry_used = NULL;
return ret;
int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
uint8_t bar_nr)
{
int ret;
char *name;
/*
* Migration compatibility dictates that this remains a 4k
* BAR with the vector table in the lower half and PBA in
* the upper half. Do not use these elsewhere!
*/
#define MSIX_EXCLUSIVE_BAR_SIZE 4096
#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0
#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)
#define MSIX_EXCLUSIVE_CAP_OFFSET 0
if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {
return -EINVAL;
}
if (asprintf(&name, "%s-msix", dev->name) == -1) {
return -ENOMEM;
}
memory_region_init(&dev->msix_exclusive_bar, name, MSIX_EXCLUSIVE_BAR_SIZE);
free(name);
ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar,
bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,
MSIX_EXCLUSIVE_CAP_OFFSET);
if (ret) {
memory_region_destroy(&dev->msix_exclusive_bar);
return ret;
}
pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,
&dev->msix_exclusive_bar);
return 0;
}
static void msix_free_irq_entries(PCIDevice *dev)
@ -317,23 +341,35 @@ static void msix_free_irq_entries(PCIDevice *dev)
}
/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
{
if (!msix_present(dev)) {
return 0;
return;
}
pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
dev->msix_cap = 0;
msix_free_irq_entries(dev);
dev->msix_entries_nr = 0;
memory_region_del_subregion(bar, &dev->msix_mmio);
memory_region_destroy(&dev->msix_mmio);
g_free(dev->msix_table_page);
dev->msix_table_page = NULL;
memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio);
memory_region_destroy(&dev->msix_pba_mmio);
g_free(dev->msix_pba);
dev->msix_pba = NULL;
memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
memory_region_destroy(&dev->msix_table_mmio);
g_free(dev->msix_table);
dev->msix_table = NULL;
g_free(dev->msix_entry_used);
dev->msix_entry_used = NULL;
dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
return 0;
return;
}
void msix_uninit_exclusive_bar(PCIDevice *dev)
{
if (msix_present(dev)) {
msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar);
memory_region_destroy(&dev->msix_exclusive_bar);
}
}
void msix_save(PCIDevice *dev, QEMUFile *f)
@ -344,8 +380,8 @@ void msix_save(PCIDevice *dev, QEMUFile *f)
return;
}
qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8);
}
/* Should be called after restoring the config space. */
@ -359,8 +395,8 @@ void msix_load(PCIDevice *dev, QEMUFile *f)
}
msix_free_irq_entries(dev);
qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8);
msix_update_function_masked(dev);
for (vector = 0; vector < n; vector++) {
@ -382,13 +418,6 @@ int msix_enabled(PCIDevice *dev)
MSIX_ENABLE_MASK);
}
/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
dev->msix_bar_size : 0;
}
/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
@ -414,7 +443,8 @@ void msix_reset(PCIDevice *dev)
msix_free_irq_entries(dev);
dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
msix_mask_all(dev, dev->msix_entries_nr);
}

19
hw/msix.h
View File

@ -4,14 +4,19 @@
#include "qemu-common.h"
#include "pci.h"
int msix_init(PCIDevice *pdev, unsigned short nentries,
MemoryRegion *bar,
unsigned bar_nr, unsigned bar_size);
void msix_set_message(PCIDevice *dev, int vector, MSIMessage msg);
int msix_init(PCIDevice *dev, unsigned short nentries,
MemoryRegion *table_bar, uint8_t table_bar_nr,
unsigned table_offset, MemoryRegion *pba_bar,
uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos);
int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
uint8_t bar_nr);
void msix_write_config(PCIDevice *pci_dev, uint32_t address,
uint32_t val, int len);
void msix_write_config(PCIDevice *dev, uint32_t address, uint32_t val, int len);
int msix_uninit(PCIDevice *d, MemoryRegion *bar);
void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar,
MemoryRegion *pba_bar);
void msix_uninit_exclusive_bar(PCIDevice *dev);
unsigned int msix_nr_vectors_allocated(const PCIDevice *dev);
@ -21,8 +26,6 @@ void msix_load(PCIDevice *dev, QEMUFile *f);
int msix_enabled(PCIDevice *dev);
int msix_present(PCIDevice *dev);
uint32_t msix_bar_size(PCIDevice *dev);
int msix_vector_use(PCIDevice *dev, unsigned vector);
void msix_vector_unuse(PCIDevice *dev, unsigned vector);
void msix_unuse_all_vectors(PCIDevice *dev);

3
hw/ne2000.c
View File

@ -744,14 +744,13 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
return 0;
}
static int pci_ne2000_exit(PCIDevice *pci_dev)
static void pci_ne2000_exit(PCIDevice *pci_dev)
{
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
NE2000State *s = &d->ne2000;
memory_region_destroy(&s->io);
qemu_del_vlan_client(&s->nic->nc);
return 0;
}
static Property ne2000_properties[] = {

54
hw/pci.c
View File

@ -849,15 +849,14 @@ static int pci_unregister_device(DeviceState *dev)
{
PCIDevice *pci_dev = PCI_DEVICE(dev);
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
int ret = 0;
if (pc->exit)
ret = pc->exit(pci_dev);
if (ret)
return ret;
pci_unregister_io_regions(pci_dev);
pci_del_option_rom(pci_dev);
if (pc->exit) {
pc->exit(pci_dev);
}
do_pci_unregister_device(pci_dev);
return 0;
}
@ -1079,6 +1078,49 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
pci_change_irq_level(pci_dev, irq_num, change);
}
/* Special hooks used by device assignment */
void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
{
assert(!bus->parent_dev);
bus->route_intx_to_irq = route_intx_to_irq;
}
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
{
PCIBus *bus;
do {
bus = dev->bus;
pin = bus->map_irq(dev, pin);
dev = bus->parent_dev;
} while (dev);
assert(bus->route_intx_to_irq);
return bus->route_intx_to_irq(bus->irq_opaque, pin);
}
void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
{
PCIDevice *dev;
PCIBus *sec;
int i;
for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
dev = bus->devices[i];
if (dev && dev->intx_routing_notifier) {
dev->intx_routing_notifier(dev);
}
QLIST_FOREACH(sec, &bus->child, sibling) {
pci_bus_fire_intx_routing_notifier(sec);
}
}
}
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
PCIINTxRoutingNotifier notifier)
{
dev->intx_routing_notifier = notifier;
}
/***********************************************************/
/* monitor info on PCI */

35
hw/pci.h
View File

@ -85,7 +85,7 @@ typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type);
typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
typedef struct PCIIORegion {
pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
@ -141,6 +141,15 @@ enum {
#define PCI_DEVICE_GET_CLASS(obj) \
OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
typedef struct PCIINTxRoute {
enum {
PCI_INTX_ENABLED,
PCI_INTX_INVERTED,
PCI_INTX_DISABLED,
} mode;
int irq;
} PCIINTxRoute;
typedef struct PCIDeviceClass {
DeviceClass parent_class;
@ -173,6 +182,7 @@ typedef struct PCIDeviceClass {
const char *romfile;
} PCIDeviceClass;
typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
MSIMessage msg);
typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
@ -222,14 +232,16 @@ struct PCIDevice {
/* MSI-X entries */
int msix_entries_nr;
/* Space to store MSIX table */
uint8_t *msix_table_page;
/* MMIO index used to map MSIX table and pending bit entries. */
MemoryRegion msix_mmio;
/* Space to store MSIX table & pending bit array */
uint8_t *msix_table;
uint8_t *msix_pba;
/* MemoryRegion container for msix exclusive BAR setup */
MemoryRegion msix_exclusive_bar;
/* Memory Regions for MSIX table and pending bit entries. */
MemoryRegion msix_table_mmio;
MemoryRegion msix_pba_mmio;
/* Reference-count for entries actually in use by driver. */
unsigned *msix_entry_used;
/* Region including the MSI-X table */
uint32_t msix_bar_size;
/* MSIX function mask set or MSIX disabled */
bool msix_function_masked;
/* Version id needed for VMState */
@ -250,6 +262,9 @@ struct PCIDevice {
MemoryRegion rom;
uint32_t rom_bar;
/* INTx routing notifier */
PCIINTxRoutingNotifier intx_routing_notifier;
/* MSI-X notifiers */
MSIVectorUseNotifier msix_vector_use_notifier;
MSIVectorReleaseNotifier msix_vector_release_notifier;
@ -278,6 +293,7 @@ MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
typedef enum {
PCI_HOTPLUG_DISABLED,
@ -306,6 +322,11 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
uint8_t devfn_min, int nirq);
void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
PCIINTxRoutingNotifier notifier);
void pci_device_reset(PCIDevice *dev);
void pci_bus_reset(PCIBus *bus);

3
hw/pci_bridge.c
View File

@ -333,7 +333,7 @@ int pci_bridge_initfn(PCIDevice *dev)
}
/* default qdev clean up function for PCI-to-PCI bridge */
int pci_bridge_exitfn(PCIDevice *pci_dev)
void pci_bridge_exitfn(PCIDevice *pci_dev)
{
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
assert(QLIST_EMPTY(&s->sec_bus.child));
@ -342,7 +342,6 @@ int pci_bridge_exitfn(PCIDevice *pci_dev)
memory_region_destroy(&s->address_space_mem);
memory_region_destroy(&s->address_space_io);
/* qbus_free() is called automatically by qdev_free() */
return 0;
}
/*

2
hw/pci_bridge.h
View File

@ -44,7 +44,7 @@ void pci_bridge_reset_reg(PCIDevice *dev);
void pci_bridge_reset(DeviceState *qdev);
int pci_bridge_initfn(PCIDevice *pci_dev);
int pci_bridge_exitfn(PCIDevice *pci_dev);
void pci_bridge_exitfn(PCIDevice *pci_dev);
/*

13
hw/pci_bridge_dev.c
View File

@ -52,7 +52,8 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
{
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
int err, ret;
int err;
pci_bridge_map_irq(br, NULL, pci_bridge_dev_map_irq_fn);
err = pci_bridge_initfn(dev);
if (err) {
@ -86,26 +87,22 @@ slotid_error:
shpc_cleanup(dev, &bridge_dev->bar);
shpc_error:
memory_region_destroy(&bridge_dev->bar);
ret = pci_bridge_exitfn(dev);
assert(!ret);
pci_bridge_exitfn(dev);
bridge_error:
return err;
}
static int pci_bridge_dev_exitfn(PCIDevice *dev)
static void pci_bridge_dev_exitfn(PCIDevice *dev)
{
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
int ret;
if (msi_present(dev)) {
msi_uninit(dev);
}
slotid_cap_cleanup(dev);
shpc_cleanup(dev, &bridge_dev->bar);
memory_region_destroy(&bridge_dev->bar);
ret = pci_bridge_exitfn(dev);
assert(!ret);
return 0;
pci_bridge_exitfn(dev);
}
static void pci_bridge_dev_write_config(PCIDevice *d,

1
hw/pci_internals.h
View File

@ -22,6 +22,7 @@ struct PCIBus {
uint8_t devfn_min;
pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq;
pci_route_irq_fn route_intx_to_irq;
pci_hotplug_fn hotplug;
DeviceState *hotplug_qdev;
void *irq_opaque;

3
hw/pcnet-pci.c
View File

@ -271,7 +271,7 @@ static void pci_pcnet_cleanup(VLANClientState *nc)
pcnet_common_cleanup(d);
}
static int pci_pcnet_uninit(PCIDevice *dev)
static void pci_pcnet_uninit(PCIDevice *dev)
{
PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);
@ -280,7 +280,6 @@ static int pci_pcnet_uninit(PCIDevice *dev)
qemu_del_timer(d->state.poll_timer);
qemu_free_timer(d->state.poll_timer);
qemu_del_vlan_client(&d->state.nic->nc);
return 0;
}
static NetClientInfo net_pci_pcnet_info = {

20
hw/piix_pci.c
View File

@ -89,6 +89,7 @@ struct PCII440FXState {
#define I440FX_SMRAM 0x72
static void piix3_set_irq(void *opaque, int pirq, int level);
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
static void piix3_write_config_xen(PCIDevice *dev,
uint32_t address, uint32_t val, int len);
@ -315,6 +316,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
pci_create_simple_multifunction(b, -1, true, "PIIX3"));
pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
PIIX_NUM_PIRQS);
pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
}
piix3->pic = pic;
*isa_bus = DO_UPCAST(ISABus, qbus,
@ -386,6 +388,22 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
piix3_set_irq_level(piix3, pirq, level);
}
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
int irq = piix3->dev.config[PIIX_PIRQC + pin];
PCIINTxRoute route;
if (irq < PIIX_NUM_PIC_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
route.mode = PCI_INTX_DISABLED;
route.irq = -1;
}
return route;
}
/* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3)
{
@ -405,6 +423,8 @@ static void piix3_write_config(PCIDevice *dev,
if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
int pic_irq;
pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
piix3_update_irq_levels(piix3);
for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);

3
hw/rtl8139.c
View File

@ -3438,7 +3438,7 @@ static void rtl8139_cleanup(VLANClientState *nc)
s->nic = NULL;
}
static int pci_rtl8139_uninit(PCIDevice *dev)
static void pci_rtl8139_uninit(PCIDevice *dev)
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
@ -3451,7 +3451,6 @@ static int pci_rtl8139_uninit(PCIDevice *dev)
qemu_del_timer(s->timer);
qemu_free_timer(s->timer);
qemu_del_vlan_client(&s->nic->nc);
return 0;
}
static NetClientInfo net_rtl8139_info = {

3
hw/usb/hcd-uhci.c
View File

@ -1269,12 +1269,11 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
return usb_uhci_common_initfn(dev);
}
static int usb_uhci_exit(PCIDevice *dev)
static void usb_uhci_exit(PCIDevice *dev)
{
UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
memory_region_destroy(&s->io_bar);
return 0;
}
static Property uhci_properties[] = {

36
hw/virtio-pci.c
View File

@ -733,13 +733,10 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)
pci_set_word(config + PCI_SUBSYSTEM_ID, vdev->device_id);
config[PCI_INTERRUPT_PIN] = 1;
memory_region_init(&proxy->msix_bar, "virtio-msix", 4096);
if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors,
&proxy->msix_bar, 1, 0)) {
pci_register_bar(&proxy->pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
&proxy->msix_bar);
} else
if (vdev->nvectors &&
msix_init_exclusive_bar(&proxy->pci_dev, vdev->nvectors, 1)) {
vdev->nvectors = 0;
}
proxy->pci_dev.config_write = virtio_write_config;
@ -782,24 +779,21 @@ static int virtio_blk_init_pci(PCIDevice *pci_dev)
return 0;
}
static int virtio_exit_pci(PCIDevice *pci_dev)
static void virtio_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
int r;
memory_region_destroy(&proxy->bar);
r = msix_uninit(pci_dev, &proxy->msix_bar);
memory_region_destroy(&proxy->msix_bar);
return r;
msix_uninit_exclusive_bar(pci_dev);
}
static int virtio_blk_exit_pci(PCIDevice *pci_dev)
static void virtio_blk_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
virtio_pci_stop_ioeventfd(proxy);
virtio_blk_exit(proxy->vdev);
return virtio_exit_pci(pci_dev);
virtio_exit_pci(pci_dev);
}
static int virtio_serial_init_pci(PCIDevice *pci_dev)
@ -824,13 +818,13 @@ static int virtio_serial_init_pci(PCIDevice *pci_dev)
return 0;
}
static int virtio_serial_exit_pci(PCIDevice *pci_dev)
static void virtio_serial_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
virtio_pci_stop_ioeventfd(proxy);
virtio_serial_exit(proxy->vdev);
return virtio_exit_pci(pci_dev);
virtio_exit_pci(pci_dev);
}
static int virtio_net_init_pci(PCIDevice *pci_dev)
@ -848,13 +842,13 @@ static int virtio_net_init_pci(PCIDevice *pci_dev)
return 0;
}
static int virtio_net_exit_pci(PCIDevice *pci_dev)
static void virtio_net_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
virtio_pci_stop_ioeventfd(proxy);
virtio_net_exit(proxy->vdev);
return virtio_exit_pci(pci_dev);
virtio_exit_pci(pci_dev);
}
static int virtio_balloon_init_pci(PCIDevice *pci_dev)
@ -875,13 +869,13 @@ static int virtio_balloon_init_pci(PCIDevice *pci_dev)
return 0;
}
static int virtio_balloon_exit_pci(PCIDevice *pci_dev)
static void virtio_balloon_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
virtio_pci_stop_ioeventfd(proxy);
virtio_balloon_exit(proxy->vdev);
return virtio_exit_pci(pci_dev);
virtio_exit_pci(pci_dev);
}
static Property virtio_blk_properties[] = {
@ -1033,12 +1027,12 @@ static int virtio_scsi_init_pci(PCIDevice *pci_dev)
return 0;
}
static int virtio_scsi_exit_pci(PCIDevice *pci_dev)
static void virtio_scsi_exit_pci(PCIDevice *pci_dev)
{
VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
virtio_scsi_exit(proxy->vdev);
return virtio_exit_pci(pci_dev);
virtio_exit_pci(pci_dev);
}
static Property virtio_scsi_properties[] = {

1
hw/virtio-pci.h
View File

@ -34,7 +34,6 @@ typedef struct {
PCIDevice pci_dev;
VirtIODevice *vdev;
MemoryRegion bar;
MemoryRegion msix_bar;
uint32_t flags;
uint32_t class_code;
uint32_t nvectors;

4
hw/wdt_i6300esb.c
View File

@ -411,13 +411,11 @@ static int i6300esb_init(PCIDevice *dev)
return 0;
}
static int i6300esb_exit(PCIDevice *dev)
static void i6300esb_exit(PCIDevice *dev)
{
I6300State *d = DO_UPCAST(I6300State, dev, dev);
memory_region_destroy(&d->io_mem);
return 0;
}
static WatchdogTimerModel model = {

8
hw/xio3130_downstream.c
View File

@ -60,7 +60,6 @@ static int xio3130_downstream_initfn(PCIDevice *d)
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
int rc;
int tmp;
rc = pci_bridge_initfn(d);
if (rc < 0) {
@ -108,12 +107,11 @@ err_pcie_cap:
err_msi:
msi_uninit(d);
err_bridge:
tmp = pci_bridge_exitfn(d);
assert(!tmp);
pci_bridge_exitfn(d);
return rc;
}
static int xio3130_downstream_exitfn(PCIDevice *d)
static void xio3130_downstream_exitfn(PCIDevice *d)
{
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
@ -123,7 +121,7 @@ static int xio3130_downstream_exitfn(PCIDevice *d)
pcie_chassis_del_slot(s);
pcie_cap_exit(d);
msi_uninit(d);
return pci_bridge_exitfn(d);
pci_bridge_exitfn(d);
}
PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,

8
hw/xio3130_upstream.c
View File

@ -56,7 +56,6 @@ static int xio3130_upstream_initfn(PCIDevice *d)
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
int rc;
int tmp;
rc = pci_bridge_initfn(d);
if (rc < 0) {
@ -95,17 +94,16 @@ err:
err_msi:
msi_uninit(d);
err_bridge:
tmp = pci_bridge_exitfn(d);
assert(!tmp);
pci_bridge_exitfn(d);
return rc;
}
static int xio3130_upstream_exitfn(PCIDevice *d)
static void xio3130_upstream_exitfn(PCIDevice *d)
{
pcie_aer_exit(d);
pcie_cap_exit(d);
msi_uninit(d);
return pci_bridge_exitfn(d);
pci_bridge_exitfn(d);
}
PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,