mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/tricore: Implement hptof insn

Browse Source 
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-8-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-08-28 13:26:47 +02:00
parent 815061b9da
commit 5e0e06d9a2
6 changed files with 58 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
target/tricore/fpu_helper.c
View File

@ -373,6 +373,42 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}
uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
{
float16 f_arg = make_float16(arg);
uint32_t result = 0;
int32_t flags = 0;
/*
* if we have any NAN we need to move the top 2 and lower 8 input mantissa
* bits to the top 2 and lower 8 output mantissa bits respectively.
* Softfloat on the other hand uses the top 10 mantissa bits.
*/
if (float16_is_any_nan(f_arg)) {
if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
flags |= float_flag_invalid;
}
result = 0;
result = float32_set_sign(result, f_arg >> 15);
result = deposit32(result, 23, 8, 0xff);
result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
} else {
set_flush_inputs_to_zero(0, &env->fp_status);
result = float16_to_float32(f_arg, true, &env->fp_status);
set_flush_inputs_to_zero(1, &env->fp_status);
flags = f_get_excp_flags(env);
}
if (flags) {
f_update_psw_flags(env, flags);
} else {
env->FPU_FS = 0;
}
return result;
}
uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);

1
target/tricore/helper.h
View File

@ -112,6 +112,7 @@ DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(ftohp, i32, env, i32)
DEF_HELPER_2(hptof, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)

7
target/tricore/translate.c
View File

@ -6267,6 +6267,13 @@ static void decode_rr_divide(DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_HPTOF:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;

1
target/tricore/tricore-opcodes.h
View File

@ -1153,6 +1153,7 @@ enum {
OPC2_32_RR_CMP_F = 0x00,
OPC2_32_RR_FTOIZ = 0x13,
OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
OPC2_32_RR_FTOQ31 = 0x11,
OPC2_32_RR_FTOQ31Z = 0x18,
OPC2_32_RR_FTOU = 0x12,

1
tests/tcg/tricore/Makefile.softmmu-target
View File

@ -17,6 +17,7 @@ TESTS += test_fmul.asm.tst
TESTS += test_ftohp.asm.tst
TESTS += test_ftoi.asm.tst
TESTS += test_ftou.asm.tst
TESTS += test_hptof.asm.tst
TESTS += test_imask.asm.tst
TESTS += test_insert.asm.tst
TESTS += test_ld_bu.asm.tst

12
tests/tcg/tricore/asm/test_hptof.S Normal file
View File

@ -0,0 +1,12 @@
#include "macros.h"
.text
.global _start
_start:
TEST_D_D(hptof, 1, 0xba190000, 0xcc0e90c8)
TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
TEST_D_D(hptof, 5, 0x3d55e000, 0x04932aaf)
TEST_PASSFAIL