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armv7m: Allow SHCSR writes to change pending and active bits

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Implement the NVIC SHCSR write behaviour which allows pending and
active status of some exceptions to be changed.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
This commit is contained in:
Peter Maydell 2017-02-28 12:08:19 +00:00
parent e13886e3a7
commit 5db53e353d
1 changed files with 11 additions and 2 deletions
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13
hw/intc/armv7m_nvic.c
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@ -755,8 +755,17 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
cpu->env.v7m.ccr = value;
break;
case 0xd24: /* System Handler Control. */
/* TODO: Real hardware allows you to set/clear the active bits
under some circumstances. We don't implement this. */
s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;