ppc/pnv: POWER9 XSCOM quad support
The POWER9 processor does not support per-core frequency control. The cores are arranged in groups of four, along with their respective L2 and L3 caches, into a structure known as a Quad. The frequency must be managed at the Quad level. Provide a basic Quad model to fake the settings done by the firmware on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special BAR setting for the TIMA area of XIVE because it resides on the same address on all chips. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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90ef386c74
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5dad902ce0
38
hw/ppc/pnv.c
38
hw/ppc/pnv.c
@ -963,6 +963,36 @@ static void pnv_chip_power9_instance_init(Object *obj)
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OBJECT(&chip9->psi), &error_abort);
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OBJECT(&chip9->psi), &error_abort);
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}
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}
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static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
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{
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PnvChip *chip = PNV_CHIP(chip9);
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const char *typename = pnv_chip_core_typename(chip);
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size_t typesize = object_type_get_instance_size(typename);
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int i;
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chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
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chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
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for (i = 0; i < chip9->nr_quads; i++) {
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char eq_name[32];
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PnvQuad *eq = &chip9->quads[i];
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PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
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int core_id = CPU_CORE(pnv_core)->core_id;
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object_initialize(eq, sizeof(*eq), TYPE_PNV_QUAD);
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snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
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object_property_add_child(OBJECT(chip), eq_name, OBJECT(eq),
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&error_fatal);
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object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
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object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
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object_unref(OBJECT(eq));
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pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
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&eq->xscom_regs);
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}
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}
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static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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{
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{
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
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PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
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@ -977,6 +1007,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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pnv_chip_quad_realize(chip9, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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/* XIVE interrupt controller (POWER9) */
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/* XIVE interrupt controller (POWER9) */
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object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
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object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
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"ic-bar", &error_fatal);
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"ic-bar", &error_fatal);
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@ -1135,7 +1171,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
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if (!pnv_chip_is_power9(chip)) {
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if (!pnv_chip_is_power9(chip)) {
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xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
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xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
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} else {
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} else {
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xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid);
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xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
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}
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}
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pnv_xscom_add_subregion(chip, xscom_core_base,
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pnv_xscom_add_subregion(chip, xscom_core_base,
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@ -327,3 +327,90 @@ static const TypeInfo pnv_core_infos[] = {
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};
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};
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DEFINE_TYPES(pnv_core_infos)
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DEFINE_TYPES(pnv_core_infos)
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/*
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* POWER9 Quads
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*/
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#define P9X_EX_NCU_SPEC_BAR 0x11010
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static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
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unsigned int width)
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{
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uint32_t offset = addr >> 3;
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uint64_t val = -1;
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switch (offset) {
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case P9X_EX_NCU_SPEC_BAR:
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case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
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val = 0;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
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offset);
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}
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return val;
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}
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static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int width)
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{
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uint32_t offset = addr >> 3;
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switch (offset) {
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case P9X_EX_NCU_SPEC_BAR:
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case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
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offset);
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}
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}
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static const MemoryRegionOps pnv_quad_xscom_ops = {
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.read = pnv_quad_xscom_read,
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.write = pnv_quad_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_quad_realize(DeviceState *dev, Error **errp)
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{
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PnvQuad *eq = PNV_QUAD(dev);
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char name[32];
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snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
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pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
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eq, name, PNV9_XSCOM_EQ_SIZE);
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}
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static Property pnv_quad_properties[] = {
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DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pnv_quad_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = pnv_quad_realize;
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dc->props = pnv_quad_properties;
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}
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static const TypeInfo pnv_quad_info = {
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.name = TYPE_PNV_QUAD,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvQuad),
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.class_init = pnv_quad_class_init,
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};
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static void pnv_core_register_types(void)
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{
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type_register_static(&pnv_quad_info);
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}
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type_init(pnv_core_register_types)
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@ -26,6 +26,7 @@
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_occ.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_xive.h"
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#include "hw/ppc/pnv_core.h"
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#define TYPE_PNV_CHIP "pnv-chip"
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#define TYPE_PNV_CHIP "pnv-chip"
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#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
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#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
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@ -89,6 +90,9 @@ typedef struct Pnv9Chip {
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Pnv9Psi psi;
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Pnv9Psi psi;
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PnvLpcController lpc;
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PnvLpcController lpc;
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PnvOCC occ;
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PnvOCC occ;
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uint32_t nr_quads;
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PnvQuad *quads;
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} Pnv9Chip;
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} Pnv9Chip;
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typedef struct PnvChipClass {
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typedef struct PnvChipClass {
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@ -58,4 +58,14 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
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return (PnvCPUState *)cpu->machine_data;
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return (PnvCPUState *)cpu->machine_data;
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}
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}
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#define TYPE_PNV_QUAD "powernv-cpu-quad"
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#define PNV_QUAD(obj) \
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OBJECT_CHECK(PnvQuad, (obj), TYPE_PNV_QUAD)
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typedef struct PnvQuad {
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DeviceState parent_obj;
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uint32_t id;
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MemoryRegion xscom_regs;
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} PnvQuad;
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#endif /* _PPC_PNV_CORE_H */
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#endif /* _PPC_PNV_CORE_H */
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@ -60,10 +60,6 @@ typedef struct PnvXScomInterfaceClass {
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_EX_SIZE 0x100000
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#define PNV_XSCOM_EX_SIZE 0x100000
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#define PNV_XSCOM_P9_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV_XSCOM_P9_EC_SIZE 0x100000
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_SIZE 0x4
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#define PNV_XSCOM_LPC_SIZE 0x4
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@ -73,6 +69,14 @@ typedef struct PnvXScomInterfaceClass {
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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#define PNV9_XSCOM_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV9_XSCOM_EC_SIZE 0x100000
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#define PNV9_XSCOM_EQ_BASE(core) \
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((uint64_t)(((core) & 0x1C) + 0x40) << 22)
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#define PNV9_XSCOM_EQ_SIZE 0x100000
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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