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virtio-pci: implement No_Soft_Reset bit

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In current code, when guest does S3, virtio-gpu are reset due to the
bit No_Soft_Reset is not set. After resetting, the display resources
of virtio-gpu are destroyed, then the display can't come back and only
show blank after resuming.

Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check
this bit, if this bit is set, the devices resetting will not be done, and
then the display can work after resuming.

No_Soft_Reset bit is implemented for all virtio devices, and was tested
only on virtio-gpu device. Set it false by default for safety.

Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com>
Message-Id: <20240606102205.114671-3-Jiqian.Chen@amd.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jiqian Chen 2024-06-06 18:22:05 +08:00 committed by Michael S. Tsirkin
parent e6c9c9e7f4
commit 5d98e18823
3 changed files with 35 additions and 0 deletions
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1
hw/core/machine.c
View File

@ -38,6 +38,7 @@ GlobalProperty hw_compat_9_0[] = {
{"arm-cpu", "backcompat-cntfrq", "true" },
{"scsi-disk-base", "migrate-emulated-scsi-request", "false" },
{"vfio-pci", "skip-vsc-check", "false" },
{ "virtio-pci", "x-pcie-pm-no-soft-reset", "off" },
};
const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);

29
hw/virtio/virtio-pci.c
View File

@ -2222,6 +2222,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
pcie_cap_lnkctl_init(pci_dev);
}
if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) {
pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
PCI_PM_CTRL_NO_SOFT_RESET);
}
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
/* Init Power Management Control Register */
pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
@ -2284,11 +2289,33 @@ static void virtio_pci_reset(DeviceState *qdev)
}
}
static bool virtio_pci_no_soft_reset(PCIDevice *dev)
{
uint16_t pmcsr;
if (!pci_is_express(dev) || !dev->exp.pm_cap) {
return false;
}
pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
/*
* When No_Soft_Reset bit is set and the device
* is in D3hot state, don't reset device
*/
return (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) &&
(pmcsr & PCI_PM_CTRL_STATE_MASK) == 3;
}
static void virtio_pci_bus_reset_hold(Object *obj, ResetType type)
{
PCIDevice *dev = PCI_DEVICE(obj);
DeviceState *qdev = DEVICE(obj);
if (virtio_pci_no_soft_reset(dev)) {
return;
}
virtio_pci_reset(qdev);
if (pci_is_express(dev)) {
@ -2328,6 +2355,8 @@ static Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, false),
DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,

5
include/hw/virtio/virtio-pci.h
View File

@ -43,6 +43,7 @@ enum {
VIRTIO_PCI_FLAG_INIT_FLR_BIT,
VIRTIO_PCI_FLAG_AER_BIT,
VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@ -79,6 +80,10 @@ enum {
/* Init Power Management */
#define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
/* Init The No_Soft_Reset bit of Power Management */
#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \
(1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT)
/* Init Function Level Reset capability */
#define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)