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target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16)

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All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
Fixes a RISU miscompare for invalid insn 0x5ef0c87a.

Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-24 16:20:20 -07:00 committed by Peter Maydell
parent c0ca7ed049
commit 5d874e5da2
1 changed files with 1 additions and 1 deletions
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target/arm/tcg/translate-a64.c
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@ -8006,7 +8006,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
case 0x2f: /* FMINP */
/* FP op, size[0] is 32 or 64 bit*/
if (!u) {
if (!dc_isar_feature(aa64_fp16, s)) {
if ((size & 1) || !dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
return;
} else {