target/ppc: booke: External interrupt cleanup
There is no LPES0 in BookE and no MSR_HV. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -838,44 +838,11 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
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trace_ppc_excp_isi(msr, env->nip);
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break;
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case POWERPC_EXCP_EXTERNAL: /* External input */
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{
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bool lpes0;
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cs = CPU(cpu);
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/*
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* Exception targeting modifiers
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*
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* LPES0 is supported on POWER7/8/9
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* LPES1 is not supported (old iSeries mode)
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*
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* On anything else, we behave as if LPES0 is 1
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* (externals don't alter MSR:HV)
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*/
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#if defined(TARGET_PPC64)
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if (excp_model == POWERPC_EXCP_POWER7 ||
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excp_model == POWERPC_EXCP_POWER8 ||
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excp_model == POWERPC_EXCP_POWER9 ||
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excp_model == POWERPC_EXCP_POWER10) {
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lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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lpes0 = true;
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}
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if (!lpes0) {
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new_msr |= (target_ulong)MSR_HVB;
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new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
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srr0 = SPR_HSRR0;
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srr1 = SPR_HSRR1;
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}
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if (env->mpic_proxy) {
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/* IACK the IRQ on delivery */
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env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
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}
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break;
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}
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case POWERPC_EXCP_ALIGN: /* Alignment exception */
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/* Get rS/rD and rA from faulting opcode */
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/*
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