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We want the argument pass to set_irq to be opaque

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piix_pci want to pass more things that the pic

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Juan Quintela 2009-08-28 15:28:17 +02:00 committed by Anthony Liguori
parent 6c009fa446
commit 5d4e84c8b9
13 changed files with 37 additions and 19 deletions
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4
hw/apb_pci.c
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@ -218,8 +218,10 @@ static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
return bus_offset + irq_num; return bus_offset + irq_num;
} }
static void pci_apb_set_irq(qemu_irq *pic, int irq_num, int level) static void pci_apb_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pic = opaque;
/* PCI IRQ map onto the first 32 INO. */ /* PCI IRQ map onto the first 32 INO. */
qemu_set_irq(pic[irq_num], level); qemu_set_irq(pic[irq_num], level);
} }

4
hw/grackle_pci.c
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@ -102,8 +102,10 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
return (irq_num + (pci_dev->devfn >> 3)) & 3; return (irq_num + (pci_dev->devfn >> 3)) & 3;
} }
static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pic = opaque;
GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level); GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
qemu_set_irq(pic[irq_num + 0x15], level); qemu_set_irq(pic[irq_num + 0x15], level);
} }

3
hw/gt64xxx.c
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@ -893,9 +893,10 @@ static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
static int pci_irq_levels[4]; static int pci_irq_levels[4];
static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level) static void pci_gt64120_set_irq(void *opaque, int irq_num, int level)
{ {
int i, pic_irq, pic_level; int i, pic_irq, pic_level;
qemu_irq *pic = opaque;
pci_irq_levels[irq_num] = level; pci_irq_levels[irq_num] = level;

6
hw/pci.c
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@ -41,7 +41,7 @@ struct PCIBus {
pci_set_irq_fn set_irq; pci_set_irq_fn set_irq;
pci_map_irq_fn map_irq; pci_map_irq_fn map_irq;
uint32_t config_reg; /* XXX: suppress */ uint32_t config_reg; /* XXX: suppress */
qemu_irq *irq_opaque; void *irq_opaque;
PCIDevice *devices[256]; PCIDevice *devices[256];
PCIDevice *parent_dev; PCIDevice *parent_dev;
PCIBus *next; PCIBus *next;
@ -100,7 +100,7 @@ static void pci_bus_reset(void *opaque)
PCIBus *pci_register_bus(DeviceState *parent, const char *name, PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
qemu_irq *pic, int devfn_min, int nirq) void *irq_opaque, int devfn_min, int nirq)
{ {
PCIBus *bus; PCIBus *bus;
static int nbus = 0; static int nbus = 0;
@ -108,7 +108,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name)); bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
bus->set_irq = set_irq; bus->set_irq = set_irq;
bus->map_irq = map_irq; bus->map_irq = map_irq;
bus->irq_opaque = pic; bus->irq_opaque = irq_opaque;
bus->devfn_min = devfn_min; bus->devfn_min = devfn_min;
bus->nirq = nirq; bus->nirq = nirq;
bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));

6
hw/pci.h
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@ -239,11 +239,11 @@ void pci_default_write_config(PCIDevice *d,
void pci_device_save(PCIDevice *s, QEMUFile *f); void pci_device_save(PCIDevice *s, QEMUFile *f);
int pci_device_load(PCIDevice *s, QEMUFile *f); int pci_device_load(PCIDevice *s, QEMUFile *f);
typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
PCIBus *pci_register_bus(DeviceState *parent, const char *name, PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
qemu_irq *pic, int devfn_min, int nirq); void *irq_opaque, int devfn_min, int nirq);
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
const char *default_devaddr); const char *default_devaddr);
@ -353,6 +353,6 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
/* sh_pci.c */ /* sh_pci.c */
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
qemu_irq *pic, int devfn_min, int nirq); void *pic, int devfn_min, int nirq);
#endif #endif

5
hw/piix_pci.c
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@ -51,7 +51,7 @@ static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
return s->config_reg; return s->config_reg;
} }
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level); static void piix3_set_irq(void *opaque, int irq_num, int level);
/* return the global irq number corresponding to a given device irq /* return the global irq number corresponding to a given device irq
pin. We could also use the bus number to have a more precise pin. We could also use the bus number to have a more precise
@ -233,9 +233,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
static PCIDevice *piix3_dev; static PCIDevice *piix3_dev;
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level) static void piix3_set_irq(void *opaque, int irq_num, int level)
{ {
int i, pic_irq, pic_level; int i, pic_irq, pic_level;
qemu_irq *pic = opaque;
pci_irq_levels[irq_num] = level; pci_irq_levels[irq_num] = level;

4
hw/ppc4xx_pci.c
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@ -304,8 +304,10 @@ static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
return slot - 1; return slot - 1;
} }
static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level) static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pci_irqs = opaque;
DPRINTF("%s: PCI irq %d\n", __func__, irq_num); DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
qemu_set_irq(pci_irqs[irq_num], level); qemu_set_irq(pci_irqs[irq_num], level);
} }

4
hw/ppce500_pci.c
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@ -253,8 +253,10 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
return ret; return ret;
} }
static void mpc85xx_pci_set_irq(qemu_irq *pic, int irq_num, int level) static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pic = opaque;
pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level); pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
qemu_set_irq(pic[irq_num], level); qemu_set_irq(pic[irq_num], level);

4
hw/prep_pci.c
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@ -124,8 +124,10 @@ static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
return (irq_num + (pci_dev->devfn >> 3)) & 1; return (irq_num + (pci_dev->devfn >> 3)) & 1;
} }
static void prep_set_irq(qemu_irq *pic, int irq_num, int level) static void prep_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pic = opaque;
qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
} }

4
hw/r2d.c
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@ -183,8 +183,10 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
} }
static void r2d_pci_set_irq(qemu_irq *p, int n, int l) static void r2d_pci_set_irq(void *opaque, int n, int l)
{ {
qemu_irq *p = opaque;
qemu_set_irq(p[n], l); qemu_set_irq(p[n], l);
} }

4
hw/sh_pci.c
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@ -168,14 +168,14 @@ static MemOp sh_pci_iop = {
}; };
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
qemu_irq *pic, int devfn_min, int nirq) void *opaque, int devfn_min, int nirq)
{ {
SHPCIC *p; SHPCIC *p;
int mem, reg, iop; int mem, reg, iop;
p = qemu_mallocz(sizeof(SHPCIC)); p = qemu_mallocz(sizeof(SHPCIC));
p->bus = pci_register_bus(NULL, "pci", p->bus = pci_register_bus(NULL, "pci",
set_irq, map_irq, pic, devfn_min, nirq); set_irq, map_irq, opaque, devfn_min, nirq);
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
-1, NULL, NULL); -1, NULL, NULL);

4
hw/unin_pci.c
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@ -141,8 +141,10 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
return (irq_num + (pci_dev->devfn >> 3)) & 3; return (irq_num + (pci_dev->devfn >> 3)) & 3;
} }
static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level) static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pic = opaque;
qemu_set_irq(pic[irq_num + 8], level); qemu_set_irq(pic[irq_num + 8], level);
} }

4
hw/versatile_pci.c
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@ -90,8 +90,10 @@ static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
return irq_num; return irq_num;
} }
static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level) static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
{ {
qemu_irq *pic = opaque;
qemu_set_irq(pic[irq_num], level); qemu_set_irq(pic[irq_num], level);
} }