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hw/nvme: split pmrmsc register into upper and lower

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The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to
make up the 64 bit logical PMRMSC register.

Make it so.

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
This commit is contained in:
Klaus Jensen 2021-07-13 14:34:52 +02:00
parent 5ffbaeed16
commit 5d45edbeac
2 changed files with 22 additions and 19 deletions
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10
hw/nvme/ctrl.c
View File

@ -5916,11 +5916,13 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
return; return;
} }
n->bar.pmrmsc = (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffffff); n->bar.pmrmscl = data;
n->pmr.cmse = false; n->pmr.cmse = false;
if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) { if (NVME_PMRMSCL_CMSE(n->bar.pmrmscl)) {
hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT; uint64_t pmrmscu = n->bar.pmrmscu;
hwaddr cba = (pmrmscu << 32) |
(NVME_PMRMSCL_CBA(n->bar.pmrmscl) << PMRMSCL_CBA_SHIFT);
if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { if (cba + int128_get64(n->pmr.dev->mr.size) < cba) {
NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1); NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1);
return; return;
@ -5936,7 +5938,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
return; return;
} }
n->bar.pmrmsc = (n->bar.pmrmsc & 0xffffffff) | (data << 32); n->bar.pmrmscu = data;
return; return;
default: default:
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,

31
include/block/nvme.h
View File

@ -26,7 +26,8 @@ typedef struct QEMU_PACKED NvmeBar {
uint32_t pmrsts; uint32_t pmrsts;
uint32_t pmrebs; uint32_t pmrebs;
uint32_t pmrswtp; uint32_t pmrswtp;
uint64_t pmrmsc; uint32_t pmrmscl;
uint32_t pmrmscu;
uint8_t css[484]; uint8_t css[484];
} NvmeBar; } NvmeBar;
@ -475,25 +476,25 @@ enum NvmePmrswtpMask {
#define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \
(pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT)
enum NvmePmrmscShift { enum NvmePmrmsclShift {
PMRMSC_CMSE_SHIFT = 1, PMRMSCL_CMSE_SHIFT = 1,
PMRMSC_CBA_SHIFT = 12, PMRMSCL_CBA_SHIFT = 12,
}; };
enum NvmePmrmscMask { enum NvmePmrmsclMask {
PMRMSC_CMSE_MASK = 0x1, PMRMSCL_CMSE_MASK = 0x1,
PMRMSC_CBA_MASK = 0xfffffffffffff, PMRMSCL_CBA_MASK = 0xfffff,
}; };
#define NVME_PMRMSC_CMSE(pmrmsc) \ #define NVME_PMRMSCL_CMSE(pmrmscl) \
((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK)
#define NVME_PMRMSC_CBA(pmrmsc) \ #define NVME_PMRMSCL_CBA(pmrmscl) \
((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK)
#define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \
(pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT)
#define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \
(pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT)
enum NvmeSglDescriptorType { enum NvmeSglDescriptorType {
NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0,