target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180211205848.4568-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4357,7 +4357,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static const ARMCPRegInfo zcr_el1_reginfo = {
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.name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
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.access = PL1_RW, .accessfn = zcr_access,
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.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
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.writefn = zcr_write, .raw_writefn = raw_write
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};
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@ -4365,7 +4365,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = {
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static const ARMCPRegInfo zcr_el2_reginfo = {
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.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
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.access = PL2_RW, .accessfn = zcr_access,
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.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
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.writefn = zcr_write, .raw_writefn = raw_write
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};
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@ -4373,14 +4373,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = {
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static const ARMCPRegInfo zcr_no_el2_reginfo = {
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.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .type = ARM_CP_64BIT,
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.access = PL2_RW,
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.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
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};
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static const ARMCPRegInfo zcr_el3_reginfo = {
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.name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
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.access = PL3_RW, .accessfn = zcr_access, .type = ARM_CP_64BIT,
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.access = PL3_RW, .accessfn = zcr_access,
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.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
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.writefn = zcr_write, .raw_writefn = raw_write
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};
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