Replace Qemu by QEMU in comments
The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
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c5ec15ea3b
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5cbdb3a34b
@ -565,7 +565,7 @@ static void ivshmem_setup_msi(IVShmemState * s) {
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msix_vector_use(&s->dev, i);
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}
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/* allocate Qemu char devices for receiving interrupts */
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/* allocate QEMU char devices for receiving interrupts */
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s->eventfd_table = g_malloc0(s->vectors * sizeof(EventfdEntry));
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}
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2
hw/pc.c
2
hw/pc.c
@ -776,7 +776,7 @@ static void load_linux(void *fw_cfg,
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}
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/* loader type */
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/* High nybble = B reserved for Qemu; low nybble is revision number.
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/* High nybble = B reserved for QEMU; low nybble is revision number.
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If this code is substantially changed, you may want to consider
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incrementing the revision. */
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if (protocol >= 0x200)
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@ -1,5 +1,5 @@
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/*
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* Qemu PowerPC 440 Bamboo board emulation
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* QEMU PowerPC 440 Bamboo board emulation
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*
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* Copyright 2007 IBM Corporation.
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* Authors:
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@ -1,5 +1,5 @@
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/*
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* Qemu PowerPC MPC8544DS board emualtion
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* QEMU PowerPC MPC8544DS board emulation
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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2
hw/ps2.c
2
hw/ps2.c
@ -88,7 +88,7 @@ typedef struct {
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typedef struct {
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PS2State common;
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int scan_enabled;
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/* Qemu uses translated PC scancodes internally. To avoid multiple
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/* QEMU uses translated PC scancodes internally. To avoid multiple
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conversions we do the translation (if any) in the PS/2 emulation
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not the keyboard controller. */
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int translate;
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12
hw/sun4m.c
12
hw/sun4m.c
@ -932,8 +932,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
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display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
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Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
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escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
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serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
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@ -1581,8 +1581,8 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
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display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
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Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
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escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
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serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
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@ -1762,8 +1762,8 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
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display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
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Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
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escc_init(hwdef->serial_base, slavio_irq[1],
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slavio_irq[1], serial_hds[0], serial_hds[1],
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ESCC_CLOCK, 1);
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@ -5152,7 +5152,7 @@ powerpc_dialect (struct disassemble_info *info)
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return dialect;
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}
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/* Qemu default */
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/* QEMU default */
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int
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print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
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{
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@ -1,7 +1,7 @@
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/* $NetBSD: queue.h,v 1.52 2009/04/20 09:56:08 mschuett Exp $ */
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/*
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* Qemu version: Copy from netbsd, removed debug code, removed some of
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* QEMU version: Copy from netbsd, removed debug code, removed some of
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* the implementations. Left in singly-linked lists, lists, simple
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* queues, and tail queues.
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*/
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@ -276,7 +276,7 @@ struct CPUAlphaState {
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target_ulong t0, t1;
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#endif
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/* Those resources are used only in Qemu core */
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/* Those resources are used only in QEMU core */
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CPU_COMMON
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int error_code;
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@ -418,7 +418,7 @@ struct CPUMIPSState {
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/* We waste some space so we can handle shadow registers like TCs. */
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TCState tcs[MIPS_SHADOW_SET_MAX];
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CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
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/* Qemu */
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/* QEMU */
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int error_code;
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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@ -233,10 +233,10 @@ enum {
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POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
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/* EOL */
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POWERPC_EXCP_NB = 96,
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/* Qemu exceptions: used internally during code translation */
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/* QEMU exceptions: used internally during code translation */
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POWERPC_EXCP_STOP = 0x200, /* stop translation */
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POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
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/* Qemu exceptions: special cases we want to stop translation */
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/* QEMU exceptions: special cases we want to stop translation */
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POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
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POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
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POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
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@ -1041,7 +1041,7 @@ struct CPUPPCState {
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/* opcode handlers */
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opc_handler_t *opcodes[0x40];
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/* Those resources are used only in Qemu core */
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/* Those resources are used only in QEMU core */
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target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
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target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
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int mmu_idx; /* precomputed MMU index to speed up mem accesses */
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@ -365,7 +365,7 @@ void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,
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tlb = &env->tlb.tlb6[nr];
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LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
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" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
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/* Invalidate any pending reference in Qemu for this virtual address */
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/* Invalidate any pending reference in QEMU for this virtual address */
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__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
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tlb->pte0 = pte0;
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tlb->pte1 = pte1;
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@ -729,7 +729,7 @@ void ppc_slb_invalidate_all (CPUPPCState *env)
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slb->esid &= ~SLB_ESID_V;
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in Qemu, we just invalidate all TLBs
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* in QEMU, we just invalidate all TLBs
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*/
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do_invalidate = 1;
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}
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@ -752,7 +752,7 @@ void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in Qemu, we just invalidate all TLBs
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* in QEMU, we just invalidate all TLBs
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*/
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tlb_flush(env, 1);
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}
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@ -2319,7 +2319,7 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
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case POWERPC_MMU_2_06:
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/* tlbie invalidate TLBs for all segments */
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/* XXX: given the fact that there are too many segments to invalidate,
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* and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
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* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
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* we just invalidate all TLBs
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*/
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tlb_flush(env, 1);
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@ -470,7 +470,7 @@ void kvm_arch_pre_run(CPUPPCState *env, struct kvm_run *run)
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int r;
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unsigned irq;
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/* PowerPC Qemu tracks the various core input pins (interrupt, critical
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/* PowerPC QEMU tracks the various core input pins (interrupt, critical
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* interrupt, reset, etc) in PPC-specific env->irq_input_state. */
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if (!cap_interrupt_level &&
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run->ready_for_interrupt_injection &&
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@ -31,7 +31,7 @@ void kvmppc_init(void)
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{
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/* XXX The only reason KVM yields control back to qemu is device IO. Since
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* an idle guest does no IO, qemu's device model will never get a chance to
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* run. So, until Qemu gains IO threads, we create this timer to ensure
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* run. So, until QEMU gains IO threads, we create this timer to ensure
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* that the device model gets a chance to run. */
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kvmppc_timer_rate = get_ticks_per_sec() / 10;
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kvmppc_timer = qemu_new_timer_ns(vm_clock, &kvmppc_timer_hack, NULL);
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@ -1796,17 +1796,17 @@ static void gen_spr_440 (CPUPPCState *env)
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static void gen_spr_40x (CPUPPCState *env)
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{
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/* Cache */
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_40x_DCCR, "DCCR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_40x_ICCR, "ICCR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, SPR_NOACCESS,
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@ -1974,7 +1974,7 @@ static void gen_spr_401_403 (CPUPPCState *env)
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SPR_NOACCESS, &spr_write_tbu,
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0x00000000);
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/* Debug */
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_403_CDBCR, "CDBCR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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@ -2012,12 +2012,12 @@ static void gen_spr_401 (CPUPPCState *env)
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_40x_sler,
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0x00000000);
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/* not emulated, as Qemu never does speculative access */
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/* not emulated, as QEMU never does speculative access */
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spr_register(env, SPR_40x_SGR, "SGR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0xFFFFFFFF);
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_40x_DCWR, "DCWR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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@ -3436,12 +3436,12 @@ static void init_proc_403GCX (CPUPPCState *env)
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gen_spr_403_real(env);
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gen_spr_403_mmu(env);
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/* Bus access control */
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/* not emulated, as Qemu never does speculative access */
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/* not emulated, as QEMU never does speculative access */
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spr_register(env, SPR_40x_SGR, "SGR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0xFFFFFFFF);
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_40x_DCWR, "DCWR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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@ -3488,12 +3488,12 @@ static void init_proc_405 (CPUPPCState *env)
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gen_spr_40x(env);
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gen_spr_405(env);
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/* Bus access control */
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/* not emulated, as Qemu never does speculative access */
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/* not emulated, as QEMU never does speculative access */
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spr_register(env, SPR_40x_SGR, "SGR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0xFFFFFFFF);
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/* not emulated, as Qemu do not emulate caches */
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/* not emulated, as QEMU do not emulate caches */
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spr_register(env, SPR_40x_DCWR, "DCWR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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@ -9442,13 +9442,13 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
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}
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if (env->irq_inputs == NULL) {
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fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
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" Attempt Qemu to crash very soon !\n");
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" Attempt QEMU to crash very soon !\n");
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}
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#endif
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if (env->check_pow == NULL) {
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fprintf(stderr, "WARNING: no power management check handler "
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"registered.\n"
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" Attempt Qemu to crash very soon !\n");
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" Attempt QEMU to crash very soon !\n");
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}
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}
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@ -772,7 +772,7 @@ QemuCocoaView *cocoaView;
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modalForWindow:normalWindow modalDelegate:self
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didEndSelector:@selector(openPanelDidEnd:returnCode:contextInfo:) contextInfo:NULL];
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} else {
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// or Launch Qemu, with the global args
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// or launch QEMU, with the global args
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[self startEmulationWithArgc:gArgc argv:(char **)gArgv];
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}
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}
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@ -219,7 +219,7 @@ static SimpleSpiceUpdate *qemu_spice_create_update(SimpleSpiceDisplay *ssd)
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/*
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* Called from spice server thread context (via interface_release_ressource)
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* We do *not* hold the global qemu mutex here, so extra care is needed
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* when calling qemu functions. Qemu interfaces used:
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* when calling qemu functions. QEMU interfaces used:
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* - g_free (underlying glibc free is re-entrant).
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*/
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void qemu_spice_destroy_update(SimpleSpiceDisplay *sdpy, SimpleSpiceUpdate *update)
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Reference in New Issue
Block a user