target-i386: Stop encoding DisasContext.mem_index
Now that we don't combine mem_index with operand size info, we don't need to encode it. Which tidies many places that access it. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
323d18769e
commit
5c42a7cd98
@ -586,7 +586,7 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
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static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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int mem_index = s->mem_index;
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switch(idx & 3) {
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case OT_BYTE:
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tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
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@ -603,7 +603,7 @@ static inline void gen_op_lds_T0_A0(DisasContext *s, int idx)
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static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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int mem_index = s->mem_index;
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switch(idx & 3) {
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case OT_BYTE:
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tcg_gen_qemu_ld8u(t0, a0, mem_index);
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@ -642,7 +642,7 @@ static inline void gen_op_ld_T1_A0(DisasContext *s, int idx)
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static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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int mem_index = s->mem_index;
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switch(idx & 3) {
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case OT_BYTE:
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tcg_gen_qemu_st8(t0, a0, mem_index);
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@ -2848,21 +2848,19 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
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static inline void gen_ldq_env_A0(DisasContext *s, int offset)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
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}
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static inline void gen_stq_env_A0(DisasContext *s, int offset)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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}
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static inline void gen_ldo_env_A0(DisasContext *s, int offset)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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int mem_index = s->mem_index;
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
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tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
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tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
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@ -2872,7 +2870,7 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
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static inline void gen_sto_env_A0(DisasContext *s, int offset)
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{
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int mem_index = (s->mem_index >> 2) - 1;
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int mem_index = s->mem_index;
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tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
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tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
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@ -3907,15 +3905,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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break;
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case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
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case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
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tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
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tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
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offsetof(XMMReg, XMM_L(0)));
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break;
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case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
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tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0, s->mem_index);
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tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
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offsetof(XMMReg, XMM_W(0)));
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break;
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@ -4375,8 +4371,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (mod == 3)
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gen_op_mov_reg_T0(ot, rm);
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else
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tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st8(cpu_T[0], cpu_A0, s->mem_index);
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break;
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case 0x15: /* pextrw */
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tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
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@ -4384,8 +4379,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (mod == 3)
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gen_op_mov_reg_T0(ot, rm);
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else
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tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st16(cpu_T[0], cpu_A0, s->mem_index);
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break;
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case 0x16:
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if (ot == OT_LONG) { /* pextrd */
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@ -4396,8 +4390,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (mod == 3)
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gen_op_mov_reg_v(ot, rm, cpu_T[0]);
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else
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tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
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} else { /* pextrq */
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#ifdef TARGET_X86_64
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tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
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@ -4407,7 +4400,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
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else
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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s->mem_index);
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#else
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goto illegal_op;
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#endif
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@ -4419,15 +4412,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (mod == 3)
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gen_op_mov_reg_T0(ot, rm);
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else
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tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st32(cpu_T[0], cpu_A0, s->mem_index);
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break;
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case 0x20: /* pinsrb */
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if (mod == 3)
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gen_op_mov_TN_reg(OT_LONG, 0, rm);
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else
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tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, s->mem_index);
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tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
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xmm_regs[reg].XMM_B(val & 15)));
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break;
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@ -4437,8 +4428,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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offsetof(CPUX86State,xmm_regs[rm]
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.XMM_L((val >> 6) & 3)));
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} else {
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
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tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
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}
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tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
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@ -4466,8 +4456,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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if (mod == 3)
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gen_op_mov_v_reg(ot, cpu_tmp0, rm);
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else
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0, s->mem_index);
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tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
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tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
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offsetof(CPUX86State,
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@ -4478,7 +4467,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
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else
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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s->mem_index);
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tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
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offsetof(CPUX86State,
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xmm_regs[reg].XMM_Q(val & 1)));
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@ -6072,8 +6061,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
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break;
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case 2:
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
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break;
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case 3:
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@ -6111,8 +6099,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
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break;
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case 2:
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
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break;
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case 3:
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@ -6133,8 +6120,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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break;
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case 2:
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gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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break;
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case 3:
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default:
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@ -6159,8 +6145,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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break;
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case 2:
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gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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break;
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case 3:
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default:
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@ -6232,14 +6217,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_helper_fpop(cpu_env);
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break;
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case 0x3d: /* fildll */
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
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break;
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case 0x3f: /* fistpll */
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gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
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(s->mem_index >> 2) - 1);
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tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, s->mem_index);
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gen_helper_fpop(cpu_env);
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break;
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default:
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@ -8320,7 +8303,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
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/* select memory access functions */
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dc->mem_index = 0;
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if (flags & HF_SOFTMMU_MASK) {
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dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
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dc->mem_index = cpu_mmu_index(env);
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}
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dc->cpuid_features = env->features[FEAT_1_EDX];
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dc->cpuid_ext_features = env->features[FEAT_1_ECX];
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