From 5bf99aa1cf67a210dd441ae4edf1e26df05360d5 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 5 Feb 2015 12:41:17 -0500 Subject: [PATCH] libqos/ahci: Add ahci_port_check_interrupts helper A helper that compares a given port's current interrupts and checks them against a supplied list of expected interrupt bits, and throws an error if they do not match. The helper then resets the requested interrupts on this port, and asserts that the interrupt register is now empty. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini Message-id: 1423158090-25580-7-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi --- tests/ahci-test.c | 13 ++----------- tests/libqos/ahci.c | 14 ++++++++++++++ tests/libqos/ahci.h | 2 ++ 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/tests/ahci-test.c b/tests/ahci-test.c index a3e8f1292b..32b6be3b92 100644 --- a/tests/ahci-test.c +++ b/tests/ahci-test.c @@ -747,19 +747,10 @@ static void ahci_test_identify(AHCIQState *ahci) while (BITSET(ahci_px_rreg(ahci, i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) { usleep(50); } + /* Check registers for post-command consistency */ ahci_port_check_error(ahci, i); - - /* Check for expected interrupts */ - reg = ahci_px_rreg(ahci, i, AHCI_PX_IS); - ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS); - ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS); /* BUG: we expect AHCI_PX_IS_DPS to be set. */ - ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS); - - /* Clear expected interrupts and assert all interrupts now cleared. */ - ahci_px_wreg(ahci, i, AHCI_PX_IS, - AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS); - g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0); + ahci_port_check_interrupts(ahci, i, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS); /* Investigate the CMD, assert that we read 512 bytes */ ahci_get_command_header(ahci, i, cx, &cmd); diff --git a/tests/libqos/ahci.c b/tests/libqos/ahci.c index 3da168abb2..ef84cc6660 100644 --- a/tests/libqos/ahci.c +++ b/tests/libqos/ahci.c @@ -333,6 +333,20 @@ void ahci_port_check_error(AHCIQState *ahci, uint8_t port) ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); } +void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, + uint32_t intr_mask) +{ + uint32_t reg; + + /* Check for expected interrupts */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + ASSERT_BIT_SET(reg, intr_mask); + + /* Clear expected interrupts and assert all interrupts now cleared. */ + ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask); + g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); +} + /* Get the command in #slot of port #port. */ void ahci_get_command_header(AHCIQState *ahci, uint8_t port, uint8_t slot, AHCICommandHeader *cmd) diff --git a/tests/libqos/ahci.h b/tests/libqos/ahci.h index af62a8a9aa..a2ffa70d22 100644 --- a/tests/libqos/ahci.h +++ b/tests/libqos/ahci.h @@ -434,6 +434,8 @@ void ahci_hba_enable(AHCIQState *ahci); unsigned ahci_port_select(AHCIQState *ahci); void ahci_port_clear(AHCIQState *ahci, uint8_t port); void ahci_port_check_error(AHCIQState *ahci, uint8_t port); +void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, + uint32_t intr_mask); void ahci_get_command_header(AHCIQState *ahci, uint8_t port, uint8_t slot, AHCICommandHeader *cmd); void ahci_set_command_header(AHCIQState *ahci, uint8_t port,