target-i386: update fp status fix
This patch introduces cpu_set_fpuc() function, which changes fpuc field of the CPU state and calls update_fp_status() function. These calls update status of softfloat library and prevent bugs caused by non-coherent rounding settings of the FPU and softfloat. v2 changes: * Added missed calls and intoduced setter function (as suggested by TeLeMan) Reviewed-by: TeLeMan <geleman@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
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@ -2580,7 +2580,7 @@ static void x86_cpu_reset(CPUState *s)
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for (i = 0; i < 8; i++) {
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env->fptags[i] = 1;
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}
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env->fpuc = 0x37f;
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cpu_set_fpuc(env, 0x37f);
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env->mxcsr = 0x1f80;
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env->xstate_bv = XSTATE_FP | XSTATE_SSE;
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@ -1251,6 +1251,7 @@ void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
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/* cc_helper.c */
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extern const uint8_t parity_table[256];
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uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
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void update_fp_status(CPUX86State *env);
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static inline uint32_t cpu_compute_eflags(CPUX86State *env)
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{
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@ -1286,6 +1287,7 @@ static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
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/* fpu_helper.c */
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void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
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void cpu_set_fpuc(CPUX86State *env, uint16_t val);
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/* svm_helper.c */
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void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
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@ -537,7 +537,7 @@ uint32_t helper_fnstcw(CPUX86State *env)
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return env->fpuc;
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}
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static void update_fp_status(CPUX86State *env)
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void update_fp_status(CPUX86State *env)
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{
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int rnd_type;
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@ -575,8 +575,7 @@ static void update_fp_status(CPUX86State *env)
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void helper_fldcw(CPUX86State *env, uint32_t val)
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{
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env->fpuc = val;
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update_fp_status(env);
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cpu_set_fpuc(env, val);
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}
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void helper_fclex(CPUX86State *env)
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@ -595,7 +594,7 @@ void helper_fninit(CPUX86State *env)
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{
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env->fpus = 0;
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env->fpstt = 0;
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env->fpuc = 0x37f;
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cpu_set_fpuc(env, 0x37f);
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env->fptags[0] = 1;
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env->fptags[1] = 1;
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env->fptags[2] = 1;
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@ -1013,11 +1012,11 @@ void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
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int i, fpus, fptag;
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if (data32) {
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env->fpuc = cpu_lduw_data(env, ptr);
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cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
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fpus = cpu_lduw_data(env, ptr + 4);
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fptag = cpu_lduw_data(env, ptr + 8);
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} else {
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env->fpuc = cpu_lduw_data(env, ptr);
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cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
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fpus = cpu_lduw_data(env, ptr + 2);
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fptag = cpu_lduw_data(env, ptr + 4);
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}
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@ -1046,7 +1045,7 @@ void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
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/* fninit */
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env->fpus = 0;
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env->fpstt = 0;
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env->fpuc = 0x37f;
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cpu_set_fpuc(env, 0x37f);
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env->fptags[0] = 1;
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env->fptags[1] = 1;
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env->fptags[2] = 1;
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@ -1157,7 +1156,7 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
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raise_exception(env, EXCP0D_GPF);
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}
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env->fpuc = cpu_lduw_data(env, ptr);
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cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
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fpus = cpu_lduw_data(env, ptr + 2);
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fptag = cpu_lduw_data(env, ptr + 4);
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env->fpstt = (fpus >> 11) & 7;
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@ -1257,6 +1256,12 @@ void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
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set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
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}
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void cpu_set_fpuc(CPUX86State *env, uint16_t val)
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{
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env->fpuc = val;
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update_fp_status(env);
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}
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void helper_ldmxcsr(CPUX86State *env, uint32_t val)
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{
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cpu_set_mxcsr(env, val);
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@ -203,7 +203,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
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case IDX_FP_REGS + 8:
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env->fpuc = ldl_p(mem_buf);
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cpu_set_fpuc(env, ldl_p(mem_buf));
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return 4;
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case IDX_FP_REGS + 9:
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tmp = ldl_p(mem_buf);
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@ -315,13 +315,13 @@ static int cpu_post_load(void *opaque, int version_id)
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env->hflags &= ~HF_CPL_MASK;
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env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
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/* XXX: restore FPU round state */
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env->fpstt = (env->fpus_vmstate >> 11) & 7;
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env->fpus = env->fpus_vmstate & ~0x3800;
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env->fptag_vmstate ^= 0xff;
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for(i = 0; i < 8; i++) {
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env->fptags[i] = (env->fptag_vmstate >> i) & 1;
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}
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update_fp_status(env);
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cpu_breakpoint_remove_all(cs, BP_CPU);
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cpu_watchpoint_remove_all(cs, BP_CPU);
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