tcg/mips: Introduce prepare_host_addr
Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
e63eed328f
commit
5b7208daa0
@ -1181,120 +1181,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
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return i;
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return i;
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}
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}
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/* We expect to use a 16-bit negative offset from ENV. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
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/*
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* Perform the tlb comparison operation.
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* The complete host address is placed in BASE.
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* Clobbers TMP0, TMP1, TMP2, TMP3.
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*/
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static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
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TCGReg addrh, MemOpIdx oi,
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tcg_insn_unit *label_ptr[2], bool is_load)
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{
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MemOp opc = get_memop(oi);
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unsigned a_bits = get_alignment_bits(opc);
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unsigned s_bits = opc & MO_SIZE;
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unsigned a_mask = (1 << a_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int add_off = offsetof(CPUTLBEntry, addend);
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int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write));
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target_ulong tlb_mask;
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
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/* Extract the TLB index from the address into TMP3. */
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tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
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/* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
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/* Load the (low-half) tlb comparator. */
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
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} else {
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tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
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: TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
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TCG_TMP0, TCG_TMP3, cmp_off);
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}
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/* Zero extend a 32-bit guest address for a 64-bit host. */
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if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
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tcg_out_ext32u(s, base, addrl);
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addrl = base;
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}
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/*
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* Mask the page bits, keeping the alignment bits to compare against.
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* For unaligned accesses, compare against the end of the access to
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* verify that it does not cross a page boundary.
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*/
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tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
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tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask);
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if (a_mask >= s_mask) {
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
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} else {
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask);
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
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}
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if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
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}
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label_ptr[0] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
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/* Load and test the high half tlb comparator. */
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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/* delay slot */
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tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
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label_ptr[1] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
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}
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/* delay slot */
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
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}
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
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TCGType ext,
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TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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void *raddr, tcg_insn_unit *label_ptr[2])
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->oi = oi;
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label->type = ext;
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label->datalo_reg = datalo;
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label->datahi_reg = datahi;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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label->raddr = tcg_splitwx_to_rx(raddr);
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label->label_ptr[0] = label_ptr[0];
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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label->label_ptr[1] = label_ptr[1];
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}
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}
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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{
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{
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const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
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const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
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@ -1403,32 +1289,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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}
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}
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#else
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#else
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static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
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TCGReg addrhi, unsigned a_bits)
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{
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unsigned a_mask = (1 << a_bits) - 1;
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TCGLabelQemuLdst *l = new_ldst_label(s);
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l->is_ld = is_ld;
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l->addrlo_reg = addrlo;
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l->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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tcg_debug_assert(a_bits < 16);
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tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
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l->label_ptr[0] = s->code_ptr;
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if (use_mips32r6_instructions) {
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tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
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} else {
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tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
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tcg_out_nop(s);
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}
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l->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
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{
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{
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void *target;
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void *target;
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@ -1478,6 +1338,154 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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}
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}
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#endif /* SOFTMMU */
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#endif /* SOFTMMU */
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typedef struct {
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TCGReg base;
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MemOp align;
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} HostAddress;
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/*
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* For softmmu, perform the TLB load and compare.
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* For useronly, perform any required alignment tests.
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* In both cases, return a TCGLabelQemuLdst structure if the slow path
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* is required and fill in @h with the host address for the fast path.
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*/
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static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGReg addrlo, TCGReg addrhi,
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MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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unsigned a_bits = get_alignment_bits(opc);
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unsigned s_bits = opc & MO_SIZE;
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unsigned a_mask = (1 << a_bits) - 1;
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TCGReg base;
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#ifdef CONFIG_SOFTMMU
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unsigned s_mask = (1 << s_bits) - 1;
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int mem_index = get_mmuidx(oi);
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int fast_off = TLB_MASK_TABLE_OFS(mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int add_off = offsetof(CPUTLBEntry, addend);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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target_ulong tlb_mask;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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base = TCG_REG_A0;
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
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QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
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/* Extract the TLB index from the address into TMP3. */
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tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo,
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TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
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/* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
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/* Load the (low-half) tlb comparator. */
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
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} else {
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tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
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: TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
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TCG_TMP0, TCG_TMP3, cmp_off);
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}
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/* Zero extend a 32-bit guest address for a 64-bit host. */
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if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
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tcg_out_ext32u(s, base, addrlo);
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addrlo = base;
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}
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/*
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* Mask the page bits, keeping the alignment bits to compare against.
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* For unaligned accesses, compare against the end of the access to
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* verify that it does not cross a page boundary.
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*/
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tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask;
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tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask);
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if (a_mask >= s_mask) {
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
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} else {
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask);
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tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
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}
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if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) {
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
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}
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
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/* Load and test the high half tlb comparator. */
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if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
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/* delay slot */
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tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
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/* Load the tlb addend for the fast path. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
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ldst->label_ptr[1] = s->code_ptr;
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tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
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}
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/* delay slot */
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tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo);
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#else
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if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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tcg_debug_assert(a_bits < 16);
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tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
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ldst->label_ptr[0] = s->code_ptr;
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if (use_mips32r6_instructions) {
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tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
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} else {
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tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
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tcg_out_nop(s);
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}
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}
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base = addrlo;
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if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
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tcg_out_ext32u(s, TCG_REG_A0, base);
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base = TCG_REG_A0;
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}
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if (guest_base) {
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if (guest_base == (int16_t)guest_base) {
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tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
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} else {
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
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TCG_GUEST_BASE_REG);
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}
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base = TCG_REG_A0;
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}
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#endif
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h->base = base;
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h->align = a_bits;
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return ldst;
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}
|
||||||
|
|
||||||
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
|
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
|
||||||
TCGReg base, MemOp opc, TCGType type)
|
TCGReg base, MemOp opc, TCGType type)
|
||||||
{
|
{
|
||||||
@ -1707,57 +1715,23 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
|||||||
MemOpIdx oi, TCGType data_type)
|
MemOpIdx oi, TCGType data_type)
|
||||||
{
|
{
|
||||||
MemOp opc = get_memop(oi);
|
MemOp opc = get_memop(oi);
|
||||||
unsigned a_bits = get_alignment_bits(opc);
|
TCGLabelQemuLdst *ldst;
|
||||||
unsigned s_bits = opc & MO_SIZE;
|
HostAddress h;
|
||||||
TCGReg base;
|
|
||||||
|
|
||||||
/*
|
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
|
||||||
* R6 removes the left/right instructions but requires the
|
|
||||||
* system to support misaligned memory accesses.
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_SOFTMMU)
|
|
||||||
tcg_insn_unit *label_ptr[2];
|
|
||||||
|
|
||||||
base = TCG_REG_A0;
|
if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
|
||||||
tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1);
|
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
|
||||||
if (use_mips32r6_instructions || a_bits >= s_bits) {
|
|
||||||
tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
|
|
||||||
} else {
|
} else {
|
||||||
tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type);
|
tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
|
||||||
}
|
}
|
||||||
add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
|
|
||||||
addrlo, addrhi, s->code_ptr, label_ptr);
|
if (ldst) {
|
||||||
#else
|
ldst->type = data_type;
|
||||||
base = addrlo;
|
ldst->datalo_reg = datalo;
|
||||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
ldst->datahi_reg = datahi;
|
||||||
tcg_out_ext32u(s, TCG_REG_A0, base);
|
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
|
||||||
base = TCG_REG_A0;
|
|
||||||
}
|
}
|
||||||
if (guest_base) {
|
|
||||||
if (guest_base == (int16_t)guest_base) {
|
|
||||||
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
|
|
||||||
} else {
|
|
||||||
tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
|
|
||||||
TCG_GUEST_BASE_REG);
|
|
||||||
}
|
|
||||||
base = TCG_REG_A0;
|
|
||||||
}
|
|
||||||
if (use_mips32r6_instructions) {
|
|
||||||
if (a_bits) {
|
|
||||||
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
|
|
||||||
}
|
|
||||||
tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
|
|
||||||
} else {
|
|
||||||
if (a_bits && a_bits != s_bits) {
|
|
||||||
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
|
|
||||||
}
|
|
||||||
if (a_bits >= s_bits) {
|
|
||||||
tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type);
|
|
||||||
} else {
|
|
||||||
tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
|
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
|
||||||
@ -1899,57 +1873,23 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
|||||||
MemOpIdx oi, TCGType data_type)
|
MemOpIdx oi, TCGType data_type)
|
||||||
{
|
{
|
||||||
MemOp opc = get_memop(oi);
|
MemOp opc = get_memop(oi);
|
||||||
unsigned a_bits = get_alignment_bits(opc);
|
TCGLabelQemuLdst *ldst;
|
||||||
unsigned s_bits = opc & MO_SIZE;
|
HostAddress h;
|
||||||
TCGReg base;
|
|
||||||
|
|
||||||
/*
|
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
|
||||||
* R6 removes the left/right instructions but requires the
|
|
||||||
* system to support misaligned memory accesses.
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_SOFTMMU)
|
|
||||||
tcg_insn_unit *label_ptr[2];
|
|
||||||
|
|
||||||
base = TCG_REG_A0;
|
if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) {
|
||||||
tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0);
|
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
|
||||||
if (use_mips32r6_instructions || a_bits >= s_bits) {
|
|
||||||
tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
|
|
||||||
} else {
|
} else {
|
||||||
tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc);
|
tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
|
||||||
}
|
}
|
||||||
add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
|
|
||||||
addrlo, addrhi, s->code_ptr, label_ptr);
|
if (ldst) {
|
||||||
#else
|
ldst->type = data_type;
|
||||||
base = addrlo;
|
ldst->datalo_reg = datalo;
|
||||||
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
|
ldst->datahi_reg = datahi;
|
||||||
tcg_out_ext32u(s, TCG_REG_A0, base);
|
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
|
||||||
base = TCG_REG_A0;
|
|
||||||
}
|
}
|
||||||
if (guest_base) {
|
|
||||||
if (guest_base == (int16_t)guest_base) {
|
|
||||||
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
|
|
||||||
} else {
|
|
||||||
tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
|
|
||||||
TCG_GUEST_BASE_REG);
|
|
||||||
}
|
|
||||||
base = TCG_REG_A0;
|
|
||||||
}
|
|
||||||
if (use_mips32r6_instructions) {
|
|
||||||
if (a_bits) {
|
|
||||||
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
|
|
||||||
}
|
|
||||||
tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
|
|
||||||
} else {
|
|
||||||
if (a_bits && a_bits != s_bits) {
|
|
||||||
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
|
|
||||||
}
|
|
||||||
if (a_bits >= s_bits) {
|
|
||||||
tcg_out_qemu_st_direct(s, datalo, datahi, base, opc);
|
|
||||||
} else {
|
|
||||||
tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_mb(TCGContext *s, TCGArg a0)
|
static void tcg_out_mb(TCGContext *s, TCGArg a0)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user