tcg/ppc: Use tcg_use_softmmu
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
e3a650cd9d
commit
5b5bd4a9b1
@ -107,9 +107,7 @@
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#define have_isel (cpuinfo & CPUINFO_ISEL)
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#define have_isel (cpuinfo & CPUINFO_ISEL)
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#ifndef CONFIG_SOFTMMU
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#define TCG_GUEST_BASE_REG TCG_REG_R30
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#define TCG_GUEST_BASE_REG 30
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#endif
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#ifdef CONFIG_DEBUG_TCG
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#ifdef CONFIG_DEBUG_TCG
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static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
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static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
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@ -2317,151 +2315,157 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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s_bits == MO_128);
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s_bits == MO_128);
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a_bits = h->aa.align;
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a_bits = h->aa.align;
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#ifdef CONFIG_SOFTMMU
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if (tcg_use_softmmu) {
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int mem_index = get_mmuidx(oi);
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int mem_index = get_mmuidx(oi);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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: offsetof(CPUTLBEntry, addr_write);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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int table_off = fast_off + offsetof(CPUTLBDescFast, table);
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off);
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/* Extract the page index, shifted into place for tlb index. */
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_out_shri32(s, TCG_REG_R0, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_shri64(s, TCG_REG_R0, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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}
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tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
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/*
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* Load the (low part) TLB comparator into TMP2.
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* For 64-bit host, always load the entire 64-bit slot for simplicity.
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* We will ignore the high bits with tcg_out_cmp(..., addr_type).
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*/
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if (TCG_TARGET_REG_BITS == 64) {
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if (cmp_off == 0) {
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tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
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} else {
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tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
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tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
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}
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} else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
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tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
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} else {
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tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
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cmp_off + 4 * HOST_BIG_ENDIAN);
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}
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/*
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* Load the TLB addend for use on the fast path.
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* Do this asap to minimize any load use delay.
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*/
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if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
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offsetof(CPUTLBEntry, addend));
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}
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/* Clear the non-page, non-alignment bits from the address in R0. */
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if (TCG_TARGET_REG_BITS == 32) {
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/*
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* We don't support unaligned accesses on 32-bits.
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* Preserve the bottom bits and thus trigger a comparison
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* failure on unaligned accesses.
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*/
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
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(32 - a_bits) & 31, 31 - s->page_bits);
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} else {
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TCGReg t = addrlo;
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/*
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* If the access is unaligned, we need to make sure we fail if we
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* cross a page boundary. The trick is to add the access size-1
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* to the address before masking the low bits. That will make the
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* address overflow to the next page if we cross a page boundary,
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* which will then force a mismatch of the TLB compare.
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*/
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if (a_bits < s_bits) {
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unsigned a_mask = (1 << a_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
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t = TCG_REG_R0;
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}
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/* Mask the address for the requested alignment. */
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if (addr_type == TCG_TYPE_I32) {
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
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(32 - a_bits) & 31, 31 - s->page_bits);
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} else if (a_bits == 0) {
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tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits);
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} else {
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tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
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64 - s->page_bits, s->page_bits - a_bits);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0);
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}
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}
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if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
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/* Low part comparison into cr7. */
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
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0, 7, TCG_TYPE_I32);
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/* Load the high part TLB comparator into TMP2. */
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
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cmp_off + 4 * !HOST_BIG_ENDIAN);
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/* Load addend, deferred for this case. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
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offsetof(CPUTLBEntry, addend));
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/* High part comparison into cr6. */
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tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32);
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/* Combine comparisons into cr7. */
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tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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} else {
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/* Full comparison into cr7. */
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, addr_type);
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}
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/* Load a pointer into the current opcode w/conditional branch-link. */
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
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h->base = TCG_REG_TMP1;
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#else
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if (a_bits) {
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ldst = new_ldst_label(s);
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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ldst->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
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tcg_debug_assert(a_bits < 16);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
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tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off);
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/* Extract the page index, shifted into place for tlb index. */
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_out_shri32(s, TCG_REG_R0, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_shri64(s, TCG_REG_R0, addrlo,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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}
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tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
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/*
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* Load the (low part) TLB comparator into TMP2.
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* For 64-bit host, always load the entire 64-bit slot for simplicity.
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* We will ignore the high bits with tcg_out_cmp(..., addr_type).
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*/
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if (TCG_TARGET_REG_BITS == 64) {
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if (cmp_off == 0) {
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tcg_out32(s, LDUX | TAB(TCG_REG_TMP2,
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TCG_REG_TMP1, TCG_REG_TMP2));
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} else {
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tcg_out32(s, ADD | TAB(TCG_REG_TMP1,
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TCG_REG_TMP1, TCG_REG_TMP2));
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tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2,
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TCG_REG_TMP1, cmp_off);
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}
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} else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
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tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2,
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TCG_REG_TMP1, TCG_REG_TMP2));
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} else {
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tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
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cmp_off + 4 * HOST_BIG_ENDIAN);
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}
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/*
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* Load the TLB addend for use on the fast path.
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* Do this asap to minimize any load use delay.
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*/
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if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
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offsetof(CPUTLBEntry, addend));
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}
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/* Clear the non-page, non-alignment bits from the address in R0. */
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if (TCG_TARGET_REG_BITS == 32) {
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/*
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* We don't support unaligned accesses on 32-bits.
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* Preserve the bottom bits and thus trigger a comparison
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* failure on unaligned accesses.
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*/
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if (a_bits < s_bits) {
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a_bits = s_bits;
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}
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
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(32 - a_bits) & 31, 31 - s->page_bits);
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} else {
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TCGReg t = addrlo;
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/*
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* If the access is unaligned, we need to make sure we fail if we
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* cross a page boundary. The trick is to add the access size-1
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* to the address before masking the low bits. That will make the
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* address overflow to the next page if we cross a page boundary,
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* which will then force a mismatch of the TLB compare.
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*/
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if (a_bits < s_bits) {
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unsigned a_mask = (1 << a_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
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t = TCG_REG_R0;
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}
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/* Mask the address for the requested alignment. */
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if (addr_type == TCG_TYPE_I32) {
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
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(32 - a_bits) & 31, 31 - s->page_bits);
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} else if (a_bits == 0) {
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tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits);
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} else {
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tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
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64 - s->page_bits, s->page_bits - a_bits);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0);
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}
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}
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if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
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/* Low part comparison into cr7. */
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
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0, 7, TCG_TYPE_I32);
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/* Load the high part TLB comparator into TMP2. */
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tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
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cmp_off + 4 * !HOST_BIG_ENDIAN);
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/* Load addend, deferred for this case. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
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offsetof(CPUTLBEntry, addend));
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/* High part comparison into cr6. */
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tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2,
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0, 6, TCG_TYPE_I32);
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/* Combine comparisons into cr7. */
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tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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} else {
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/* Full comparison into cr7. */
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tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
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0, 7, addr_type);
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}
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/* Load a pointer into the current opcode w/conditional branch-link. */
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ldst->label_ptr[0] = s->code_ptr;
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
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tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
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}
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h->base = guest_base ? TCG_GUEST_BASE_REG : 0;
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h->base = TCG_REG_TMP1;
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#endif
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} else {
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if (a_bits) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* We are expecting a_bits to max out at 7, much lower than ANDI. */
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tcg_debug_assert(a_bits < 16);
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tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
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ldst->label_ptr[0] = s->code_ptr;
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tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
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}
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h->base = guest_base ? TCG_GUEST_BASE_REG : 0;
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}
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if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
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if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
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/* Zero-extend the guest address for use in the host address. */
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/* Zero-extend the guest address for use in the host address. */
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@ -2695,12 +2699,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
|
|||||||
}
|
}
|
||||||
tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
|
tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
|
||||||
|
|
||||||
#ifndef CONFIG_SOFTMMU
|
if (!tcg_use_softmmu && guest_base) {
|
||||||
if (guest_base) {
|
|
||||||
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
|
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
|
||||||
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
|
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
|
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
|
||||||
tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
|
tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user