arm hw/: Don't use CPUState
Scripted conversion: for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c hw/strongarm.h hw/versatilepb.c hw/vexpress.c hw/xilinx_zynq.c ; do sed -i "s/CPUState/CPUARMState/g" $file done Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
parent
8b2aee2959
commit
5ae9330682
@ -16,7 +16,7 @@
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/* The CPU is also modeled as an interrupt controller. */
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/* The CPU is also modeled as an interrupt controller. */
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#define ARM_PIC_CPU_IRQ 0
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#define ARM_PIC_CPU_IRQ 0
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#define ARM_PIC_CPU_FIQ 1
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#define ARM_PIC_CPU_FIQ 1
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qemu_irq *arm_pic_init_cpu(CPUState *env);
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qemu_irq *arm_pic_init_cpu(CPUARMState *env);
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/* armv7m.c */
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/* armv7m.c */
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qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
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qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
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@ -50,16 +50,16 @@ struct arm_boot_info {
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* perform any necessary CPU reset handling and set the PC for thei
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* perform any necessary CPU reset handling and set the PC for thei
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* secondary CPUs to point at this boot blob.
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* secondary CPUs to point at this boot blob.
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*/
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*/
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void (*write_secondary_boot)(CPUState *env,
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void (*write_secondary_boot)(CPUARMState *env,
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const struct arm_boot_info *info);
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const struct arm_boot_info *info);
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void (*secondary_cpu_reset_hook)(CPUState *env,
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void (*secondary_cpu_reset_hook)(CPUARMState *env,
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const struct arm_boot_info *info);
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const struct arm_boot_info *info);
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/* Used internally by arm_boot.c */
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/* Used internally by arm_boot.c */
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int is_linux;
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int is_linux;
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target_phys_addr_t initrd_size;
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target_phys_addr_t initrd_size;
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target_phys_addr_t entry;
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target_phys_addr_t entry;
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};
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};
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void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
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void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info);
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/* Multiplication factor to convert from system clock ticks to qemu timer
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/* Multiplication factor to convert from system clock ticks to qemu timer
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ticks. */
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ticks. */
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@ -59,7 +59,7 @@ static uint32_t smpboot[] = {
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0 /* bootreg: Boot register address is held here */
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0 /* bootreg: Boot register address is held here */
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};
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};
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static void default_write_secondary(CPUState *env,
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static void default_write_secondary(CPUARMState *env,
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const struct arm_boot_info *info)
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const struct arm_boot_info *info)
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{
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{
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int n;
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int n;
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@ -72,7 +72,7 @@ static void default_write_secondary(CPUState *env,
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info->smp_loader_start);
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info->smp_loader_start);
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}
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}
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static void default_reset_secondary(CPUState *env,
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static void default_reset_secondary(CPUARMState *env,
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const struct arm_boot_info *info)
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const struct arm_boot_info *info)
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{
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{
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stl_phys_notdirty(info->smp_bootreg_addr, 0);
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stl_phys_notdirty(info->smp_bootreg_addr, 0);
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@ -274,7 +274,7 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
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static void do_cpu_reset(void *opaque)
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static void do_cpu_reset(void *opaque)
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{
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{
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CPUState *env = opaque;
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CPUARMState *env = opaque;
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const struct arm_boot_info *info = env->boot_info;
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const struct arm_boot_info *info = env->boot_info;
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cpu_state_reset(env);
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cpu_state_reset(env);
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@ -300,7 +300,7 @@ static void do_cpu_reset(void *opaque)
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}
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}
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}
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}
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void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
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void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
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{
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{
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int kernel_size;
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int kernel_size;
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int initrd_size;
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int initrd_size;
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@ -13,7 +13,7 @@
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/* Input 0 is IRQ and input 1 is FIQ. */
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/* Input 0 is IRQ and input 1 is FIQ. */
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static void arm_pic_cpu_handler(void *opaque, int irq, int level)
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static void arm_pic_cpu_handler(void *opaque, int irq, int level)
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{
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{
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CPUState *env = (CPUState *)opaque;
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CPUARMState *env = (CPUARMState *)opaque;
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switch (irq) {
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switch (irq) {
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case ARM_PIC_CPU_IRQ:
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case ARM_PIC_CPU_IRQ:
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if (level)
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if (level)
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@ -32,7 +32,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
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}
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}
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}
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}
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qemu_irq *arm_pic_init_cpu(CPUState *env)
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qemu_irq *arm_pic_init_cpu(CPUARMState *env)
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{
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{
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return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
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return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
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}
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}
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@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
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static void armv7m_reset(void *opaque)
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static void armv7m_reset(void *opaque)
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{
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{
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cpu_state_reset((CPUState *)opaque);
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cpu_state_reset((CPUARMState *)opaque);
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}
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}
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/* Init CPU and memory for a v7-M based board.
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/* Init CPU and memory for a v7-M based board.
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@ -160,7 +160,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
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int flash_size, int sram_size,
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int flash_size, int sram_size,
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const char *kernel_filename, const char *cpu_model)
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const char *kernel_filename, const char *cpu_model)
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{
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{
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CPUState *env;
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CPUARMState *env;
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DeviceState *nvic;
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DeviceState *nvic;
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/* FIXME: make this local state. */
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/* FIXME: make this local state. */
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static qemu_irq pic[64];
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static qemu_irq pic[64];
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@ -83,7 +83,7 @@ typedef struct Exynos4210Irq {
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} Exynos4210Irq;
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} Exynos4210Irq;
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typedef struct Exynos4210State {
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typedef struct Exynos4210State {
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CPUState * env[EXYNOS4210_NCPUS];
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CPUARMState * env[EXYNOS4210_NCPUS];
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Exynos4210Irq irqs;
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Exynos4210Irq irqs;
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qemu_irq *irq_table;
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qemu_irq *irq_table;
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@ -37,12 +37,12 @@
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/* Board init. */
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/* Board init. */
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static void highbank_cpu_reset(void *opaque)
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static void highbank_cpu_reset(void *opaque)
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{
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{
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CPUState *env = opaque;
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CPUARMState *env = opaque;
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env->cp15.c15_config_base_address = GIC_BASE_ADDR;
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env->cp15.c15_config_base_address = GIC_BASE_ADDR;
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}
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}
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static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
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static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
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{
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{
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int n;
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int n;
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uint32_t smpboot[] = {
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uint32_t smpboot[] = {
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@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
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rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
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}
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}
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static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
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static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
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{
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{
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switch (info->nb_cpus) {
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switch (info->nb_cpus) {
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case 4:
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case 4:
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@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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const char *initrd_filename, const char *cpu_model)
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{
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{
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CPUState *env = NULL;
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CPUARMState *env = NULL;
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DeviceState *dev;
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DeviceState *dev;
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SysBusDevice *busdev;
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SysBusDevice *busdev;
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qemu_irq *irqp;
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qemu_irq *irqp;
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@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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const char *initrd_filename, const char *cpu_model)
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{
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{
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CPUState *env;
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CPUARMState *env;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
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MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
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@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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const char *initrd_filename, const char *cpu_model)
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{
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{
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CPUState *env;
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CPUARMState *env;
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qemu_irq *cpu_pic;
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qemu_irq *cpu_pic;
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qemu_irq pic[32];
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qemu_irq pic[32];
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DeviceState *dev;
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DeviceState *dev;
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@ -813,7 +813,7 @@ struct omap_mpu_state_s {
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omap3630,
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omap3630,
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} mpu_model;
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} mpu_model;
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CPUState *env;
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CPUARMState *env;
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qemu_irq *drq;
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qemu_irq *drq;
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6
hw/pxa.h
6
hw/pxa.h
@ -65,11 +65,11 @@
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# define PXA2XX_INTERNAL_SIZE 0x40000
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# define PXA2XX_INTERNAL_SIZE 0x40000
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/* pxa2xx_pic.c */
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/* pxa2xx_pic.c */
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env);
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/* pxa2xx_gpio.c */
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/* pxa2xx_gpio.c */
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, DeviceState *pic, int lines);
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CPUARMState *env, DeviceState *pic, int lines);
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
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/* pxa2xx_dma.c */
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/* pxa2xx_dma.c */
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@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState;
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typedef struct PXA2xxFIrState PXA2xxFIrState;
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typedef struct PXA2xxFIrState PXA2xxFIrState;
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typedef struct {
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typedef struct {
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CPUState *env;
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CPUARMState *env;
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DeviceState *pic;
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DeviceState *pic;
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qemu_irq reset;
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qemu_irq reset;
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MemoryRegion sdram;
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MemoryRegion sdram;
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@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo {
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qemu_irq irq0, irq1, irqX;
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qemu_irq irq0, irq1, irqX;
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int lines;
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int lines;
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int ncpu;
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int ncpu;
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CPUState *cpu_env;
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CPUARMState *cpu_env;
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/* XXX: GNU C vectors are more suitable */
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/* XXX: GNU C vectors are more suitable */
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uint32_t ilevel[PXA2XX_GPIO_BANKS];
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uint32_t ilevel[PXA2XX_GPIO_BANKS];
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@ -249,7 +249,7 @@ static const MemoryRegionOps pxa_gpio_ops = {
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};
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};
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, DeviceState *pic, int lines)
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CPUARMState *env, DeviceState *pic, int lines)
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{
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{
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DeviceState *dev;
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DeviceState *dev;
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@ -34,7 +34,7 @@
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typedef struct {
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typedef struct {
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion iomem;
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MemoryRegion iomem;
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CPUState *cpu_env;
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CPUARMState *cpu_env;
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uint32_t int_enabled[2];
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uint32_t int_enabled[2];
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uint32_t int_pending[2];
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uint32_t int_pending[2];
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uint32_t is_fiq[2];
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uint32_t is_fiq[2];
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@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
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return 0;
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return 0;
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}
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}
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env)
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{
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{
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
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@ -128,7 +128,7 @@ static void realview_init(ram_addr_t ram_size,
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const char *initrd_filename, const char *cpu_model,
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const char *initrd_filename, const char *cpu_model,
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enum realview_board_type board_type)
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enum realview_board_type board_type)
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{
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{
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CPUState *env = NULL;
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CPUARMState *env = NULL;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
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MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
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MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
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MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
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@ -53,7 +53,7 @@ enum {
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};
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};
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typedef struct {
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typedef struct {
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CPUState *env;
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CPUARMState *env;
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MemoryRegion sdram;
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MemoryRegion sdram;
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DeviceState *pic;
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DeviceState *pic;
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DeviceState *gpio;
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DeviceState *gpio;
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@ -167,7 +167,7 @@ static void versatile_init(ram_addr_t ram_size,
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const char *initrd_filename, const char *cpu_model,
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const char *initrd_filename, const char *cpu_model,
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int board_id)
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int board_id)
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{
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{
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CPUState *env;
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CPUARMState *env;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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qemu_irq *cpu_pic;
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qemu_irq *cpu_pic;
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@ -159,7 +159,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
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const char *cpu_model,
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const char *cpu_model,
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qemu_irq *pic, uint32_t *proc_id)
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qemu_irq *pic, uint32_t *proc_id)
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{
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{
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CPUState *env = NULL;
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CPUARMState *env = NULL;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *lowram = g_new(MemoryRegion, 1);
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MemoryRegion *lowram = g_new(MemoryRegion, 1);
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@ -259,7 +259,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
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qemu_irq *pic, uint32_t *proc_id)
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qemu_irq *pic, uint32_t *proc_id)
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{
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{
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int n;
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int n;
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CPUState *env = NULL;
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CPUARMState *env = NULL;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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@ -50,7 +50,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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const char *initrd_filename, const char *cpu_model)
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{
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{
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CPUState *env = NULL;
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CPUARMState *env = NULL;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
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MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
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||||||
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
|
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
|
||||||
|
Loading…
Reference in New Issue
Block a user