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arm hw/: Don't use CPUState

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Scripted conversion:
  for file in hw/arm-misc.h hw/arm_boot.c hw/arm_pic.c hw/armv7m.c hw/exynos4210.h hw/highbank.c hw/integratorcp.c hw/musicpal.c hw/omap.h hw/pxa.h hw/pxa2xx_gpio.c hw/pxa2xx_pic.c hw/realview.c hw/strongarm.h hw/versatilepb.c hw/vexpress.c  hw/xilinx_zynq.c ; do
    sed -i "s/CPUState/CPUARMState/g" $file
  done

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:23 +01:00
parent 8b2aee2959
commit 5ae9330682
17 changed files with 33 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/arm-misc.h
View File

@ -16,7 +16,7 @@
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUState *env);
qemu_irq *arm_pic_init_cpu(CPUARMState *env);
/* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
@ -50,16 +50,16 @@ struct arm_boot_info {
* perform any necessary CPU reset handling and set the PC for thei
* secondary CPUs to point at this boot blob.
*/
void (*write_secondary_boot)(CPUState *env,
void (*write_secondary_boot)(CPUARMState *env,
const struct arm_boot_info *info);
void (*secondary_cpu_reset_hook)(CPUState *env,
void (*secondary_cpu_reset_hook)(CPUARMState *env,
const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
target_phys_addr_t entry;
};
void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info);
/* Multiplication factor to convert from system clock ticks to qemu timer
ticks. */

8
hw/arm_boot.c
View File

@ -59,7 +59,7 @@ static uint32_t smpboot[] = {
0 /* bootreg: Boot register address is held here */
};
static void default_write_secondary(CPUState *env,
static void default_write_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
int n;
@ -72,7 +72,7 @@ static void default_write_secondary(CPUState *env,
info->smp_loader_start);
}
static void default_reset_secondary(CPUState *env,
static void default_reset_secondary(CPUARMState *env,
const struct arm_boot_info *info)
{
stl_phys_notdirty(info->smp_bootreg_addr, 0);
@ -274,7 +274,7 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo)
static void do_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUARMState *env = opaque;
const struct arm_boot_info *info = env->boot_info;
cpu_state_reset(env);
@ -300,7 +300,7 @@ static void do_cpu_reset(void *opaque)
}
}
void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info)
{
int kernel_size;
int initrd_size;

4
hw/arm_pic.c
View File

@ -13,7 +13,7 @@
/* Input 0 is IRQ and input 1 is FIQ. */
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
CPUState *env = (CPUState *)opaque;
CPUARMState *env = (CPUARMState *)opaque;
switch (irq) {
case ARM_PIC_CPU_IRQ:
if (level)
@ -32,7 +32,7 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
}
}
qemu_irq *arm_pic_init_cpu(CPUState *env)
qemu_irq *arm_pic_init_cpu(CPUARMState *env)
{
return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
}

4
hw/armv7m.c
View File

@ -149,7 +149,7 @@ static void armv7m_bitband_init(void)
static void armv7m_reset(void *opaque)
{
cpu_state_reset((CPUState *)opaque);
cpu_state_reset((CPUARMState *)opaque);
}
/* Init CPU and memory for a v7-M based board.
@ -160,7 +160,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
CPUState *env;
CPUARMState *env;
DeviceState *nvic;
/* FIXME: make this local state. */
static qemu_irq pic[64];

2
hw/exynos4210.h
View File

@ -83,7 +83,7 @@ typedef struct Exynos4210Irq {
} Exynos4210Irq;
typedef struct Exynos4210State {
CPUState * env[EXYNOS4210_NCPUS];
CPUARMState * env[EXYNOS4210_NCPUS];
Exynos4210Irq irqs;
qemu_irq *irq_table;

8
hw/highbank.c
View File

@ -37,12 +37,12 @@
/* Board init. */
static void highbank_cpu_reset(void *opaque)
{
CPUState *env = opaque;
CPUARMState *env = opaque;
env->cp15.c15_config_base_address = GIC_BASE_ADDR;
}
static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
int n;
uint32_t smpboot[] = {
@ -66,7 +66,7 @@ static void hb_write_secondary(CPUState *env, const struct arm_boot_info *info)
rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}
static void hb_reset_secondary(CPUState *env, const struct arm_boot_info *info)
static void hb_reset_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
switch (info->nb_cpus) {
case 4:
@ -196,7 +196,7 @@ static void highbank_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env = NULL;
CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;

2
hw/integratorcp.c
View File

@ -443,7 +443,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUARMState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);

2
hw/musicpal.c
View File

@ -1513,7 +1513,7 @@ static void musicpal_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
CPUARMState *env;
qemu_irq *cpu_pic;
qemu_irq pic[32];
DeviceState *dev;

2
hw/omap.h
View File

@ -813,7 +813,7 @@ struct omap_mpu_state_s {
omap3630,
} mpu_model;
CPUState *env;
CPUARMState *env;
qemu_irq *drq;

6
hw/pxa.h
View File

@ -65,11 +65,11 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env);
/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, DeviceState *pic, int lines);
CPUARMState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;
typedef struct {
CPUState *env;
CPUARMState *env;
DeviceState *pic;
qemu_irq reset;
MemoryRegion sdram;

4
hw/pxa2xx_gpio.c
View File

@ -20,7 +20,7 @@ struct PXA2xxGPIOInfo {
qemu_irq irq0, irq1, irqX;
int lines;
int ncpu;
CPUState *cpu_env;
CPUARMState *cpu_env;
/* XXX: GNU C vectors are more suitable */
uint32_t ilevel[PXA2XX_GPIO_BANKS];
@ -249,7 +249,7 @@ static const MemoryRegionOps pxa_gpio_ops = {
};
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
CPUState *env, DeviceState *pic, int lines)
CPUARMState *env, DeviceState *pic, int lines)
{
DeviceState *dev;

4
hw/pxa2xx_pic.c
View File

@ -34,7 +34,7 @@
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
CPUState *cpu_env;
CPUARMState *cpu_env;
uint32_t int_enabled[2];
uint32_t int_pending[2];
uint32_t is_fiq[2];
@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
return 0;
}
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env)
{
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));

2
hw/realview.c
View File

@ -128,7 +128,7 @@ static void realview_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
enum realview_board_type board_type)
{
CPUState *env = NULL;
CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);

2
hw/strongarm.h
View File

@ -53,7 +53,7 @@ enum {
};
typedef struct {
CPUState *env;
CPUARMState *env;
MemoryRegion sdram;
DeviceState *pic;
DeviceState *gpio;

2
hw/versatilepb.c
View File

@ -167,7 +167,7 @@ static void versatile_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model,
int board_id)
{
CPUState *env;
CPUARMState *env;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_pic;

4
hw/vexpress.c
View File

@ -159,7 +159,7 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
const char *cpu_model,
qemu_irq *pic, uint32_t *proc_id)
{
CPUState *env = NULL;
CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *lowram = g_new(MemoryRegion, 1);
@ -259,7 +259,7 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
qemu_irq *pic, uint32_t *proc_id)
{
int n;
CPUState *env = NULL;
CPUARMState *env = NULL;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);

2
hw/xilinx_zynq.c
View File

@ -50,7 +50,7 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env = NULL;
CPUARMState *env = NULL;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);