Name the magic constants, wrap long lines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3751 c046a42c-6fe2-441c-8c8c-71466251a162
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188
hw/esp.c
188
hw/esp.c
@ -32,8 +32,8 @@
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//#define DEBUG_ESP
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/*
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
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* produced as NCR89C100. See
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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@ -81,12 +81,51 @@ struct ESPState {
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void *dma_opaque;
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};
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#define ESP_TCLO 0x0
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#define ESP_TCMID 0x1
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#define ESP_FIFO 0x2
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#define ESP_CMD 0x3
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#define ESP_RSTAT 0x4
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#define ESP_WBUSID 0x4
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#define ESP_RINTR 0x5
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#define ESP_WSEL 0x5
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#define ESP_RSEQ 0x6
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#define ESP_WSYNTP 0x6
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#define ESP_RFLAGS 0x7
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#define ESP_WSYNO 0x7
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#define ESP_CFG1 0x8
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#define ESP_RRES1 0x9
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#define ESP_WCCF 0x9
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#define ESP_RRES2 0xa
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#define ESP_WTEST 0xa
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#define ESP_CFG2 0xb
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#define ESP_CFG3 0xc
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#define ESP_RES3 0xd
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#define ESP_TCHI 0xe
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#define ESP_RES4 0xf
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#define CMD_DMA 0x80
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#define CMD_CMD 0x7f
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#define CMD_NOP 0x00
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#define CMD_FLUSH 0x01
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#define CMD_RESET 0x02
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#define CMD_BUSRESET 0x03
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#define CMD_TI 0x10
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#define CMD_ICCS 0x11
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#define CMD_MSGACC 0x12
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#define CMD_SATN 0x1a
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#define CMD_SELATN 0x42
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#define CMD_SELATNS 0x43
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#define CMD_ENSEL 0x44
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#define STAT_DO 0x00
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MI 0x06
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#define STAT_MO 0x07
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#define STAT_PIO_MASK 0x06
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#define STAT_TC 0x10
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#define STAT_PE 0x20
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@ -101,13 +140,19 @@ struct ESPState {
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#define SEQ_0 0x0
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#define SEQ_CD 0x4
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#define CFG1_RESREPT 0x40
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#define CFG2_MASK 0x15
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#define TCHI_FAS100A 0x4
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static int get_cmd(ESPState *s, uint8_t *buf)
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{
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uint32_t dmalen;
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int target;
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dmalen = s->rregs[0] | (s->rregs[1] << 8);
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target = s->wregs[4] & 7;
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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target = s->wregs[ESP_WBUSID] & 7;
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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if (s->dma) {
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espdma_memory_read(s->dma_opaque, buf, dmalen);
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@ -129,9 +174,9 @@ static int get_cmd(ESPState *s, uint8_t *buf)
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if (target >= MAX_DISKS || !s->scsi_dev[target]) {
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// No such drive
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s->rregs[4] = STAT_IN;
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s->rregs[5] = INTR_DC;
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s->rregs[6] = SEQ_0;
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s->rregs[ESP_RSTAT] = STAT_IN;
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RSEQ] = SEQ_0;
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qemu_irq_raise(s->irq);
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return 0;
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}
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@ -149,19 +194,19 @@ static void do_cmd(ESPState *s, uint8_t *buf)
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datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
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s->ti_size = datalen;
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if (datalen != 0) {
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s->rregs[4] = STAT_IN | STAT_TC;
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s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC;
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s->dma_left = 0;
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s->dma_counter = 0;
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if (datalen > 0) {
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s->rregs[4] |= STAT_DI;
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s->rregs[ESP_RSTAT] |= STAT_DI;
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scsi_read_data(s->current_dev, 0);
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} else {
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s->rregs[4] |= STAT_DO;
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s->rregs[ESP_RSTAT] |= STAT_DO;
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scsi_write_data(s->current_dev, 0);
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}
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}
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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qemu_irq_raise(s->irq);
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}
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@ -181,9 +226,9 @@ static void handle_satn_stop(ESPState *s)
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if (s->cmdlen) {
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DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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s->do_cmd = 1;
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s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_CD;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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qemu_irq_raise(s->irq);
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}
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}
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@ -195,26 +240,26 @@ static void write_response(ESPState *s)
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s->ti_buf[1] = 0;
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if (s->dma) {
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espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
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s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[5] = INTR_BS | INTR_FC;
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s->rregs[6] = SEQ_CD;
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s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_ST;
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s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
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s->rregs[ESP_RSEQ] = SEQ_CD;
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} else {
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s->ti_size = 2;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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s->rregs[7] = 2;
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s->rregs[ESP_RFLAGS] = 2;
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}
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qemu_irq_raise(s->irq);
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}
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static void esp_dma_done(ESPState *s)
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{
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s->rregs[4] |= STAT_IN | STAT_TC;
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s->rregs[5] = INTR_BS;
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s->rregs[6] = 0;
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s->rregs[7] = 0;
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s->rregs[0] = 0;
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s->rregs[1] = 0;
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s->rregs[ESP_RSTAT] |= STAT_IN | STAT_TC;
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s->rregs[ESP_RINTR] = INTR_BS;
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s->rregs[ESP_RSEQ] = 0;
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s->rregs[ESP_RFLAGS] = 0;
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s->rregs[ESP_TCLO] = 0;
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s->rregs[ESP_TCMID] = 0;
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qemu_irq_raise(s->irq);
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}
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@ -287,7 +332,7 @@ static void esp_command_complete(void *opaque, int reason, uint32_t tag,
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if (arg)
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DPRINTF("Command failed\n");
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s->sense = arg;
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s->rregs[4] = STAT_ST;
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s->rregs[ESP_RSTAT] = STAT_ST;
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esp_dma_done(s);
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s->current_dev = NULL;
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} else {
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@ -308,7 +353,7 @@ static void handle_ti(ESPState *s)
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{
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uint32_t dmalen, minlen;
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dmalen = s->rregs[0] | (s->rregs[1] << 8);
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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if (dmalen==0) {
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dmalen=0x10000;
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}
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@ -323,7 +368,7 @@ static void handle_ti(ESPState *s)
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DPRINTF("Transfer Information len %d\n", minlen);
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if (s->dma) {
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s->dma_left = minlen;
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s->rregs[4] &= ~STAT_TC;
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s->rregs[ESP_RSTAT] &= ~STAT_TC;
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esp_do_dma(s);
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} else if (s->do_cmd) {
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DPRINTF("command len %d\n", s->cmdlen);
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@ -341,7 +386,7 @@ static void esp_reset(void *opaque)
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memset(s->rregs, 0, ESP_REGS);
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memset(s->wregs, 0, ESP_REGS);
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s->rregs[0x0e] = 0x4; // Indicate fas100a
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s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
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s->ti_size = 0;
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s->ti_rptr = 0;
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s->ti_wptr = 0;
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@ -363,16 +408,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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saddr = (addr & ESP_MASK) >> 2;
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DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
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switch (saddr) {
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case 2:
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// FIFO
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case ESP_FIFO:
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if (s->ti_size > 0) {
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s->ti_size--;
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if ((s->rregs[4] & 6) == 0) {
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if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
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/* Data in/out. */
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fprintf(stderr, "esp: PIO data read not implemented\n");
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s->rregs[2] = 0;
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s->rregs[ESP_FIFO] = 0;
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} else {
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s->rregs[2] = s->ti_buf[s->ti_rptr++];
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s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
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}
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qemu_irq_raise(s->irq);
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}
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@ -381,10 +425,9 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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s->ti_wptr = 0;
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}
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break;
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case 5:
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// interrupt
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case ESP_RINTR:
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// Clear interrupt/error status bits
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s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE);
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s->rregs[ESP_RSTAT] &= ~(STAT_IN | STAT_GE | STAT_PE);
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qemu_irq_lower(s->irq);
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break;
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default:
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@ -399,17 +442,17 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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uint32_t saddr;
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saddr = (addr & ESP_MASK) >> 2;
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DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
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DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
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val);
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switch (saddr) {
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case 0:
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case 1:
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s->rregs[4] &= ~STAT_TC;
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case ESP_TCLO:
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case ESP_TCMID:
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s->rregs[ESP_RSTAT] &= ~STAT_TC;
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break;
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case 2:
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// FIFO
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case ESP_FIFO:
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if (s->do_cmd) {
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s->cmdbuf[s->cmdlen++] = val & 0xff;
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} else if ((s->rregs[4] & 6) == 0) {
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} else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
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uint8_t buf;
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buf = val & 0xff;
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s->ti_size--;
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@ -419,63 +462,62 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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s->ti_buf[s->ti_wptr++] = val & 0xff;
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}
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break;
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case 3:
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case ESP_CMD:
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s->rregs[saddr] = val;
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// Command
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if (val & 0x80) {
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if (val & CMD_DMA) {
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s->dma = 1;
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/* Reload DMA counter. */
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s->rregs[0] = s->wregs[0];
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s->rregs[1] = s->wregs[1];
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s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
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s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
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} else {
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s->dma = 0;
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}
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switch(val & 0x7f) {
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case 0:
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switch(val & CMD_CMD) {
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case CMD_NOP:
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DPRINTF("NOP (%2.2x)\n", val);
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break;
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case 1:
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case CMD_FLUSH:
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DPRINTF("Flush FIFO (%2.2x)\n", val);
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//s->ti_size = 0;
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s->rregs[5] = INTR_FC;
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s->rregs[6] = 0;
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s->rregs[ESP_RINTR] = INTR_FC;
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s->rregs[ESP_RSEQ] = 0;
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break;
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case 2:
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case CMD_RESET:
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DPRINTF("Chip reset (%2.2x)\n", val);
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esp_reset(s);
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break;
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case 3:
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case CMD_BUSRESET:
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DPRINTF("Bus reset (%2.2x)\n", val);
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s->rregs[5] = INTR_RST;
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if (!(s->wregs[8] & 0x40)) {
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s->rregs[ESP_RINTR] = INTR_RST;
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if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
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qemu_irq_raise(s->irq);
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}
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break;
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case 0x10:
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case CMD_TI:
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handle_ti(s);
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break;
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case 0x11:
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case CMD_ICCS:
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DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
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write_response(s);
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break;
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case 0x12:
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case CMD_MSGACC:
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DPRINTF("Message Accepted (%2.2x)\n", val);
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write_response(s);
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s->rregs[5] = INTR_DC;
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s->rregs[6] = 0;
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s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RSEQ] = 0;
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break;
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case 0x1a:
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case CMD_SATN:
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DPRINTF("Set ATN (%2.2x)\n", val);
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break;
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case 0x42:
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case CMD_SELATN:
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DPRINTF("Set ATN (%2.2x)\n", val);
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handle_satn(s);
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break;
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case 0x43:
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case CMD_SELATNS:
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DPRINTF("Set ATN & stop (%2.2x)\n", val);
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handle_satn_stop(s);
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break;
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case 0x44:
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case CMD_ENSEL:
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DPRINTF("Enable selection (%2.2x)\n", val);
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break;
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default:
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@ -483,17 +525,17 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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break;
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}
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break;
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case 4 ... 7:
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case ESP_WBUSID ... ESP_WSYNO:
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break;
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case 8:
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case ESP_CFG1:
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s->rregs[saddr] = val;
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break;
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case 9 ... 10:
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case ESP_WCCF ... ESP_WTEST:
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break;
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case 11:
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s->rregs[saddr] = val & 0x15;
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case ESP_CFG2:
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s->rregs[saddr] = val & CFG2_MASK;
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break;
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case 12 ... 15:
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case ESP_CFG3 ... ESP_RES4:
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s->rregs[saddr] = val;
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break;
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default:
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32
hw/iommu.c
32
hw/iommu.c
@ -61,12 +61,16 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
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#define IOMMU_AFSR (0x1000 >> 2)
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#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
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#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
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transaction */
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#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
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12.8 us. */
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#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
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acknowledge */
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#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
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#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
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#define IOMMU_AFSR_RESV 0x00f00000 /* Reserved, forced to 0x8 by hardware */
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#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
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hardware */
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#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
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#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
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#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
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@ -77,7 +81,8 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
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#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
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#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
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#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
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#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
|
||||
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
|
||||
bypass enabled */
|
||||
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
|
||||
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
|
||||
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
|
||||
@ -91,7 +96,8 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
|
||||
|
||||
/* The format of an iopte in the page tables */
|
||||
#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
|
||||
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
|
||||
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
|
||||
Viking/MXCC) */
|
||||
#define IOPTE_WRITE 0x00000004 /* Writeable */
|
||||
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
|
||||
#define IOPTE_WAZ 0x00000001 /* Write as zeros */
|
||||
@ -122,7 +128,8 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
|
||||
uint32_t val)
|
||||
{
|
||||
IOMMUState *s = opaque;
|
||||
target_phys_addr_t saddr;
|
||||
@ -235,10 +242,11 @@ static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
|
||||
return pa;
|
||||
}
|
||||
|
||||
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
|
||||
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
|
||||
int is_write)
|
||||
{
|
||||
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
|
||||
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) |
|
||||
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
|
||||
IOMMU_AFSR_FAV;
|
||||
if (!is_write)
|
||||
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
|
||||
@ -311,7 +319,7 @@ static void iommu_reset(void *opaque)
|
||||
s->iostart = 0;
|
||||
s->regs[IOMMU_CTRL] = s->version;
|
||||
s->regs[IOMMU_ARBEN] = IOMMU_MID;
|
||||
s->regs[IOMMU_AFSR] = 0x00800000;
|
||||
s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
|
||||
}
|
||||
|
||||
void *iommu_init(target_phys_addr_t addr, uint32_t version)
|
||||
@ -326,7 +334,8 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
|
||||
s->addr = addr;
|
||||
s->version = version;
|
||||
|
||||
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
|
||||
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
|
||||
iommu_mem_write, s);
|
||||
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
|
||||
|
||||
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
|
||||
@ -334,4 +343,3 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
|
||||
iommu_reset(s);
|
||||
return s;
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user