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macio: convert pmac_ide_ops from old_mmio

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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Mark Cave-Ayland 2017-09-20 07:20:01 +01:00 committed by David Gibson
parent 5261158d21
commit 5abdf67009
1 changed files with 78 additions and 109 deletions
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187
hw/ide/macio.c
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@ -255,102 +255,37 @@ static void pmac_ide_flush(DBDMA_io *io)
} }
/* PowerMac IDE memory IO */ /* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque, static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
hwaddr addr, uint32_t val)
{ {
MACIOIDEState *d = opaque; MACIOIDEState *d = opaque;
uint64_t retval = 0xffffffff;
int reg = addr >> 4;
addr = (addr & 0xFFF) >> 4; switch (reg) {
switch (addr) { case 0x0:
case 1 ... 7: if (size == 2) {
ide_ioport_write(&d->bus, addr, val); retval = ide_data_readw(&d->bus, 0);
break; } else if (size == 4) {
case 8: retval = ide_data_readl(&d->bus, 0);
case 22:
ide_cmd_write(&d->bus, 0, val);
break;
default:
break;
}
}
static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
addr = (addr & 0xFFF) >> 4;
switch (addr) {
case 1 ... 7:
retval = ide_ioport_read(&d->bus, addr);
break;
case 8:
case 22:
retval = ide_status_read(&d->bus, 0);
break;
default:
retval = 0xFF;
break;
}
return retval;
}
static void pmac_ide_writew (void *opaque,
hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
addr = (addr & 0xFFF) >> 4;
val = bswap16(val);
if (addr == 0) {
ide_data_writew(&d->bus, 0, val);
}
}
static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
addr = (addr & 0xFFF) >> 4;
if (addr == 0) {
retval = ide_data_readw(&d->bus, 0);
} else {
retval = 0xFFFF;
}
retval = bswap16(retval);
return retval;
}
static void pmac_ide_writel (void *opaque,
hwaddr addr, uint32_t val)
{
MACIOIDEState *d = opaque;
addr = (addr & 0xFFF) >> 4;
val = bswap32(val);
if (addr == 0) {
ide_data_writel(&d->bus, 0, val);
} else if (addr == 0x20) {
d->timing_reg = val;
} else if (addr == 0x30) {
if (val & 0x80000000u) {
d->irq_reg &= 0x7fffffff;
} }
} break;
} case 0x1 ... 0x7:
if (size == 1) {
static uint32_t pmac_ide_readl (void *opaque,hwaddr addr) retval = ide_ioport_read(&d->bus, reg);
{ }
uint32_t retval; break;
MACIOIDEState *d = opaque; case 0x8:
case 0x16:
addr = (addr & 0xFFF) >> 4; if (size == 1) {
if (addr == 0) { retval = ide_status_read(&d->bus, 0);
retval = ide_data_readl(&d->bus, 0); }
} else if (addr == 0x20) { break;
retval = d->timing_reg; case 0x20:
} else if (addr == 0x30) { if (size == 4) {
retval = d->timing_reg;
}
break;
case 0x30:
/* This is an interrupt state register that only exists /* This is an interrupt state register that only exists
* in the KeyLargo and later variants. Bit 0x8000_0000 * in the KeyLargo and later variants. Bit 0x8000_0000
* latches the DMA interrupt and has to be written to * latches the DMA interrupt and has to be written to
@ -358,28 +293,62 @@ static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
* interrupt. MacOS X relies on this and will hang if * interrupt. MacOS X relies on this and will hang if
* we don't provide at least the disk interrupt * we don't provide at least the disk interrupt
*/ */
retval = d->irq_reg; if (size == 4) {
} else { retval = d->irq_reg;
retval = 0xFFFFFFFF; }
break;
} }
retval = bswap32(retval);
return retval; return retval;
} }
static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
MACIOIDEState *d = opaque;
int reg = addr >> 4;
switch (reg) {
case 0x0:
if (size == 2) {
ide_data_writew(&d->bus, 0, val);
} else if (size == 4) {
ide_data_writel(&d->bus, 0, val);
}
break;
case 0x1 ... 0x7:
if (size == 1) {
ide_ioport_write(&d->bus, reg, val);
}
break;
case 0x8:
case 0x16:
if (size == 1) {
ide_cmd_write(&d->bus, 0, val);
}
break;
case 0x20:
if (size == 4) {
d->timing_reg = val;
}
break;
case 0x30:
if (size == 4) {
if (val & 0x80000000u) {
d->irq_reg &= 0x7fffffff;
}
}
break;
}
}
static const MemoryRegionOps pmac_ide_ops = { static const MemoryRegionOps pmac_ide_ops = {
.old_mmio = { .read = pmac_ide_read,
.write = { .write = pmac_ide_write,
pmac_ide_writeb, .valid.min_access_size = 1,
pmac_ide_writew, .valid.max_access_size = 4,
pmac_ide_writel, .endianness = DEVICE_LITTLE_ENDIAN,
},
.read = {
pmac_ide_readb,
pmac_ide_readw,
pmac_ide_readl,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static const VMStateDescription vmstate_pmac = { static const VMStateDescription vmstate_pmac = {