mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/riscv: Allow setting a two-stage lookup in the virt status

Browse Source 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis 2020-08-12 12:13:16 -07:00
parent 18df0b4695
commit 5a894dd770
3 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/riscv/cpu.h
View File

@ -321,6 +321,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

1
target/riscv/cpu_bits.h
View File

@ -467,6 +467,7 @@
* page table fault. * page table fault.
*/ */
#define FORCE_HS_EXCEP 2 #define FORCE_HS_EXCEP 2
#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */ /* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000 #define SATP32_MODE 0x80000000

18
target/riscv/cpu_helper.c
View File

@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable); env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
} }
bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
return false;
}
return get_field(env->virt, HS_TWO_STAGE);
}
void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
{
if (!riscv_has_ext(env, RVH)) {
return;
}
env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
}
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{ {
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;