mirror of https://gitlab.com/qemu-project/qemu
Sparc64: enable real access to PCI configuration space
Leave the bogus access method used by OpenBIOS in place for now. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
parent
c3863f2544
commit
5a5d4a7651
88
hw/apb_pci.c
88
hw/apb_pci.c
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@ -104,6 +104,82 @@ static CPUReadMemoryFunc * const apb_config_read[] = {
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&apb_config_readl,
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&apb_config_readl,
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};
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};
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static void apb_pci_config_write(APBState *s, target_phys_addr_t addr,
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uint32_t val, int size)
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{
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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pci_data_write(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31), val,
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size);
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}
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static uint32_t apb_pci_config_read(APBState *s, target_phys_addr_t addr,
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int size)
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{
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uint32_t ret;
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ret = pci_data_read(s->host_state.bus, (addr & 0x00ffffff) | (1u << 31),
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size);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
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return ret;
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}
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static void apb_pci_config_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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APBState *s = opaque;
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apb_pci_config_write(s, addr, val, 4);
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}
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static void apb_pci_config_writew(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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APBState *s = opaque;
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apb_pci_config_write(s, addr, val, 2);
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}
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static void apb_pci_config_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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APBState *s = opaque;
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apb_pci_config_write(s, addr, val, 1);
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}
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static uint32_t apb_pci_config_readl(void *opaque, target_phys_addr_t addr)
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{
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APBState *s = opaque;
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return apb_pci_config_read(s, addr, 4);
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}
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static uint32_t apb_pci_config_readw(void *opaque, target_phys_addr_t addr)
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{
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APBState *s = opaque;
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return apb_pci_config_read(s, addr, 2);
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}
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static uint32_t apb_pci_config_readb(void *opaque, target_phys_addr_t addr)
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{
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APBState *s = opaque;
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return apb_pci_config_read(s, addr, 1);
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}
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static CPUWriteMemoryFunc * const apb_pci_config_writes[] = {
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&apb_pci_config_writel,
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&apb_pci_config_writew,
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&apb_pci_config_writeb,
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};
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static CPUReadMemoryFunc * const apb_pci_config_reads[] = {
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&apb_pci_config_readl,
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&apb_pci_config_readw,
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&apb_pci_config_readb,
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};
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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uint32_t val)
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{
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{
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@ -217,10 +293,12 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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sysbus_mmio_map(s, 0, special_base);
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sysbus_mmio_map(s, 0, special_base);
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/* pci_ioport */
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/* pci_ioport */
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sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
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sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
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/* mem_config: XXX size should be 4G-prom */
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/* mem_config: XXX should not exist */
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sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
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sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
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/* mem_config: XXX size should be 4G-prom */
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sysbus_mmio_map(s, 3, special_base + 0x1000010ULL);
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/* mem_data */
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/* mem_data */
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sysbus_mmio_map(s, 3, mem_base);
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sysbus_mmio_map(s, 4, mem_base);
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d = FROM_SYSBUS(APBState, s);
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d = FROM_SYSBUS(APBState, s);
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_apb_set_irq, pci_pbm_map_irq, pic,
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pci_apb_set_irq, pci_pbm_map_irq, pic,
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@ -248,7 +326,7 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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{
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{
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APBState *s;
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APBState *s;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
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int pci_mem_config, pci_mem_data, apb_config, pci_ioport, pci_config;
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s = FROM_SYSBUS(APBState, dev);
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s = FROM_SYSBUS(APBState, dev);
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/* apb_config */
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/* apb_config */
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@ -262,6 +340,10 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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/* mem_config */
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/* mem_config */
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pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
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pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
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sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
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sysbus_init_mmio(dev, 0x10ULL, pci_mem_config);
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/* pci_config */
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pci_config = cpu_register_io_memory(apb_pci_config_reads,
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apb_pci_config_writes, s);
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sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
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/* mem_data */
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/* mem_data */
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pci_mem_data = pci_host_data_register_mmio(&s->host_state);
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pci_mem_data = pci_host_data_register_mmio(&s->host_state);
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sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
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sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
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