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target/arm: Split out do_neon_ddda 

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-88-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:03:53 -07:00 committed by Peter Maydell
parent 64ea60869b
commit 5a46304c03
1 changed files with 38 additions and 52 deletions
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90
target/arm/translate-neon.c
View File

@ -151,6 +151,36 @@ static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var)
}
}
static bool do_neon_ddda(DisasContext *s, int q, int vd, int vn, int vm,
int data, gen_helper_gvec_4 *fn_gvec)
{
/* UNDEF accesses to D16-D31 if they don't exist. */
if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) {
return false;
}
/*
* UNDEF accesses to odd registers for each bit of Q.
* Q will be 0b111 for all Q-reg instructions, otherwise
* when we have mixed Q- and D-reg inputs.
*/
if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
int opr_sz = q ? 16 : 8;
tcg_gen_gvec_4_ool(vfp_reg_offset(1, vd),
vfp_reg_offset(1, vn),
vfp_reg_offset(1, vm),
vfp_reg_offset(1, vd),
opr_sz, opr_sz, data, fn_gvec);
return true;
}
static bool do_neon_ddda_fpst(DisasContext *s, int q, int vd, int vn, int vm,
int data, ARMFPStatusFlavour fp_flavour,
gen_helper_gvec_4_ptr *fn_gvec_ptr)
@ -241,35 +271,13 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
{
int opr_sz;
gen_helper_gvec_4 *fn_gvec;
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
if ((a->vn | a->vm | a->vd) & a->q) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
opr_sz = (1 + a->q) * 8;
fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn),
vfp_reg_offset(1, a->vm),
vfp_reg_offset(1, a->vd),
opr_sz, opr_sz, 0, fn_gvec);
return true;
return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
a->u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b);
}
static bool trans_VFML(DisasContext *s, arg_VFML *a)
@ -323,35 +331,13 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
{
gen_helper_gvec_4 *fn_gvec;
int opr_sz;
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn) & 0x10)) {
return false;
}
if ((a->vd | a->vn) & a->q) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
opr_sz = (1 + a->q) * 8;
tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn),
vfp_reg_offset(1, a->vm),
vfp_reg_offset(1, a->vd),
opr_sz, opr_sz, a->index, fn_gvec);
return true;
return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
a->u
? gen_helper_gvec_udot_idx_b
: gen_helper_gvec_sdot_idx_b);
}
static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)