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target/mips: Clean up handling of CP0 register 27

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Clean up handling of CP0 register 27.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-27-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:50 +02:00
parent dbbf08b289
commit 5a10873d7d
1 changed files with 4 additions and 16 deletions
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20
target/mips/translate.c
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@ -7466,10 +7466,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@ -8224,10 +8221,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@ -8955,10 +8949,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@ -9694,10 +9685,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
case 0:
case 1:
case 2:
case 3:
case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;