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target/mips: Migrate TLB MemoryMapID register

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Include CP0 MemoryMapID register in migration state.

Fixes: 99029be1c2 ("target/mips: Add implementation of GINVT instruction")
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
Message-ID: <AM9PR09MB4851FB6034EDB7FA191BA47E84402@AM9PR09MB4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Yongbok Kim 2017-03-24 08:54:49 -03:00 committed by Philippe Mathieu-Daudé
parent 92ec780519
commit 59e7592756
1 changed files with 5 additions and 2 deletions
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7
target/mips/sysemu/machine.c
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@ -142,6 +142,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size,
qemu_get_betls(f, &v->VPN);
qemu_get_be32s(f, &v->PageMask);
qemu_get_be16s(f, &v->ASID);
qemu_get_be32s(f, &v->MMID);
qemu_get_be16s(f, &flags);
v->G = (flags >> 10) & 1;
v->C0 = (flags >> 7) & 3;
@ -167,6 +168,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
r4k_tlb_t *v = pv;
uint16_t asid = v->ASID;
uint32_t mmid = v->MMID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
@ -183,6 +185,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
qemu_put_betls(f, &v->VPN);
qemu_put_be32s(f, &v->PageMask);
qemu_put_be16s(f, &asid);
qemu_put_be32s(f, &mmid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
@ -204,8 +207,8 @@ static const VMStateInfo vmstate_info_tlb = {
static const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
.version_id = 2,
.minimum_version_id = 2,
.version_id = 3,
.minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),