accel/tcg: Reorg system mode store helpers
Instead of trying to unify all operations on uint64_t, use mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
8cfdacaa16
commit
592134617c
@ -2532,322 +2532,300 @@ store_memop(void *haddr, uint64_t val, MemOp op)
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}
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}
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static void full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr);
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static void __attribute__((noinline))
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store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
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uintptr_t retaddr, size_t size, uintptr_t mmu_idx,
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bool big_endian)
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/**
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* do_st_mmio_leN:
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* @env: cpu context
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* @p: translation parameters
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* @val_le: data to store
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* @mmu_idx: virtual address context
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* @ra: return address into tcg generated code, or 0
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*
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* Store @p->size bytes at @p->addr, which is memory-mapped i/o.
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* The bytes to store are extracted in little-endian order from @val_le;
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* return the bytes of @val_le beyond @p->size that have not been stored.
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*/
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static uint64_t do_st_mmio_leN(CPUArchState *env, MMULookupPageData *p,
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uint64_t val_le, int mmu_idx, uintptr_t ra)
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{
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uintptr_t index, index2;
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CPUTLBEntry *entry, *entry2;
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target_ulong page1, page2, tlb_addr, tlb_addr2;
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MemOpIdx oi;
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size_t size2;
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int i;
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CPUTLBEntryFull *full = p->full;
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target_ulong addr = p->addr;
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int i, size = p->size;
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/*
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* Ensure the second page is in the TLB. Note that the first page
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* is already guaranteed to be filled, and that the second page
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* cannot evict the first. An exception to this rule is PAGE_WRITE_INV
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* handling: the first page could have evicted itself.
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*/
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page1 = addr & TARGET_PAGE_MASK;
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page2 = (addr + size) & TARGET_PAGE_MASK;
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size2 = (addr + size) & ~TARGET_PAGE_MASK;
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index2 = tlb_index(env, mmu_idx, page2);
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entry2 = tlb_entry(env, mmu_idx, page2);
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tlb_addr2 = tlb_addr_write(entry2);
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if (page1 != page2 && !tlb_hit_page(tlb_addr2, page2)) {
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if (!victim_tlb_hit(env, mmu_idx, index2, MMU_DATA_STORE, page2)) {
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tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index2 = tlb_index(env, mmu_idx, page2);
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entry2 = tlb_entry(env, mmu_idx, page2);
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}
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tlb_addr2 = tlb_addr_write(entry2);
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QEMU_IOTHREAD_LOCK_GUARD();
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for (i = 0; i < size; i++, val_le >>= 8) {
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io_writex(env, full, mmu_idx, val_le, addr + i, ra, MO_UB);
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}
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return val_le;
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}
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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tlb_addr = tlb_addr_write(entry);
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/**
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* do_st_bytes_leN:
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* @p: translation parameters
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* @val_le: data to store
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*
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* Store @p->size bytes at @p->haddr, which is RAM.
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* The bytes to store are extracted in little-endian order from @val_le;
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* return the bytes of @val_le beyond @p->size that have not been stored.
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*/
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static uint64_t do_st_bytes_leN(MMULookupPageData *p, uint64_t val_le)
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{
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uint8_t *haddr = p->haddr;
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int i, size = p->size;
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/*
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* Handle watchpoints. Since this may trap, all checks
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* must happen before any store.
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*/
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if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
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cpu_check_watchpoint(env_cpu(env), addr, size - size2,
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env_tlb(env)->d[mmu_idx].fulltlb[index].attrs,
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BP_MEM_WRITE, retaddr);
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}
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if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) {
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cpu_check_watchpoint(env_cpu(env), page2, size2,
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env_tlb(env)->d[mmu_idx].fulltlb[index2].attrs,
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BP_MEM_WRITE, retaddr);
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for (i = 0; i < size; i++, val_le >>= 8) {
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haddr[i] = val_le;
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}
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return val_le;
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}
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/*
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* XXX: not efficient, but simple.
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* This loop must go in the forward direction to avoid issues
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* with self-modifying code in Windows 64-bit.
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*/
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oi = make_memop_idx(MO_UB, mmu_idx);
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if (big_endian) {
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for (i = 0; i < size; ++i) {
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/* Big-endian extract. */
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uint8_t val8 = val >> (((size - 1) * 8) - (i * 8));
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full_stb_mmu(env, addr + i, val8, oi, retaddr);
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}
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/*
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* Wrapper for the above.
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*/
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static uint64_t do_st_leN(CPUArchState *env, MMULookupPageData *p,
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uint64_t val_le, int mmu_idx, uintptr_t ra)
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{
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if (unlikely(p->flags & TLB_MMIO)) {
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return do_st_mmio_leN(env, p, val_le, mmu_idx, ra);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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return val_le >> (p->size * 8);
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} else {
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for (i = 0; i < size; ++i) {
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/* Little-endian extract. */
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uint8_t val8 = val >> (i * 8);
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full_stb_mmu(env, addr + i, val8, oi, retaddr);
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}
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return do_st_bytes_leN(p, val_le);
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}
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}
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static inline void QEMU_ALWAYS_INLINE
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store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr, MemOp op)
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static void do_st_1(CPUArchState *env, MMULookupPageData *p, uint8_t val,
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int mmu_idx, uintptr_t ra)
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{
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const unsigned a_bits = get_alignment_bits(get_memop(oi));
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const size_t size = memop_size(op);
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uintptr_t mmu_idx = get_mmuidx(oi);
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uintptr_t index;
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CPUTLBEntry *entry;
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target_ulong tlb_addr;
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void *haddr;
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tcg_debug_assert(mmu_idx < NB_MMU_MODES);
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/* Handle CPU specific unaligned behaviour */
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if (addr & ((1 << a_bits) - 1)) {
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cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, MO_UB);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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*(uint8_t *)p->haddr = val;
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}
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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tlb_addr = tlb_addr_write(entry);
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/* If the TLB entry is for a different page, reload and try again. */
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if (!tlb_hit(tlb_addr, addr)) {
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if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE,
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addr & TARGET_PAGE_MASK)) {
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tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE,
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mmu_idx, retaddr);
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index = tlb_index(env, mmu_idx, addr);
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entry = tlb_entry(env, mmu_idx, addr);
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}
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tlb_addr = tlb_addr_write(entry) & ~TLB_INVALID_MASK;
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}
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/* Handle anything that isn't just a straight memory access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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CPUTLBEntryFull *full;
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bool need_swap;
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/* For anything that is unaligned, recurse through byte stores. */
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if ((addr & (size - 1)) != 0) {
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goto do_unaligned_access;
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}
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full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
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/* Handle watchpoints. */
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if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
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/* On watchpoint hit, this will longjmp out. */
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cpu_check_watchpoint(env_cpu(env), addr, size,
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full->attrs, BP_MEM_WRITE, retaddr);
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}
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need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
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/* Handle I/O access. */
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if (tlb_addr & TLB_MMIO) {
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io_writex(env, full, mmu_idx, val, addr, retaddr,
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op ^ (need_swap * MO_BSWAP));
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return;
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}
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/* Ignore writes to ROM. */
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if (unlikely(tlb_addr & TLB_DISCARD_WRITE)) {
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return;
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}
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/* Handle clean RAM pages. */
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if (tlb_addr & TLB_NOTDIRTY) {
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notdirty_write(env_cpu(env), addr, size, full, retaddr);
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}
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haddr = (void *)((uintptr_t)addr + entry->addend);
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/*
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* Keep these two store_memop separate to ensure that the compiler
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* is able to fold the entire function to a single instruction.
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* There is a build-time assert inside to remind you of this. ;-)
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*/
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if (unlikely(need_swap)) {
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store_memop(haddr, val, op ^ MO_BSWAP);
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} else {
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store_memop(haddr, val, op);
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}
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (size > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + size - 1
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>= TARGET_PAGE_SIZE)) {
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do_unaligned_access:
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store_helper_unaligned(env, addr, val, retaddr, size,
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mmu_idx, memop_big_endian(op));
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return;
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}
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haddr = (void *)((uintptr_t)addr + entry->addend);
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store_memop(haddr, val, op);
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}
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static void __attribute__((noinline))
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full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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static void do_st_2(CPUArchState *env, MMULookupPageData *p, uint16_t val,
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int mmu_idx, MemOp memop, uintptr_t ra)
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{
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validate_memop(oi, MO_UB);
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store_helper(env, addr, val, oi, retaddr, MO_UB);
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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/* Swap to host endian if necessary, then store. */
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if (memop & MO_BSWAP) {
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val = bswap16(val);
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}
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store_memop(p->haddr, val, MO_UW);
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}
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}
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static void do_st_4(CPUArchState *env, MMULookupPageData *p, uint32_t val,
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int mmu_idx, MemOp memop, uintptr_t ra)
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{
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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/* Swap to host endian if necessary, then store. */
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if (memop & MO_BSWAP) {
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val = bswap32(val);
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}
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store_memop(p->haddr, val, MO_UL);
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}
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}
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static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val,
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int mmu_idx, MemOp memop, uintptr_t ra)
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{
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if (unlikely(p->flags & TLB_MMIO)) {
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io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop);
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} else if (unlikely(p->flags & TLB_DISCARD_WRITE)) {
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/* nothing */
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} else {
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/* Swap to host endian if necessary, then store. */
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if (memop & MO_BSWAP) {
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val = bswap64(val);
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}
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store_memop(p->haddr, val, MO_UQ);
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}
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}
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void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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MemOpIdx oi, uintptr_t ra)
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{
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full_stb_mmu(env, addr, val, oi, retaddr);
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MMULookupLocals l;
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bool crosspage;
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validate_memop(oi, MO_UB);
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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tcg_debug_assert(!crosspage);
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do_st_1(env, &l.page[0], val, l.mmu_idx, ra);
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}
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static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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static void do_st2_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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MemOpIdx oi, uintptr_t ra)
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{
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validate_memop(oi, MO_LEUW);
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store_helper(env, addr, val, oi, retaddr, MO_LEUW);
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MMULookupLocals l;
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bool crosspage;
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uint8_t a, b;
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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do_st_2(env, &l.page[0], val, l.mmu_idx, l.memop, ra);
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return;
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}
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if ((l.memop & MO_BSWAP) == MO_LE) {
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a = val, b = val >> 8;
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} else {
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b = val, a = val >> 8;
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}
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do_st_1(env, &l.page[0], a, l.mmu_idx, ra);
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do_st_1(env, &l.page[1], b, l.mmu_idx, ra);
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}
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void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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full_le_stw_mmu(env, addr, val, oi, retaddr);
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}
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static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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validate_memop(oi, MO_BEUW);
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store_helper(env, addr, val, oi, retaddr, MO_BEUW);
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validate_memop(oi, MO_LEUW);
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do_st2_mmu(env, addr, val, oi, retaddr);
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}
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void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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full_be_stw_mmu(env, addr, val, oi, retaddr);
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validate_memop(oi, MO_BEUW);
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do_st2_mmu(env, addr, val, oi, retaddr);
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}
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static void full_le_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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static void do_st4_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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MemOpIdx oi, uintptr_t ra)
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{
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validate_memop(oi, MO_LEUL);
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store_helper(env, addr, val, oi, retaddr, MO_LEUL);
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MMULookupLocals l;
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bool crosspage;
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crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
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if (likely(!crosspage)) {
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do_st_4(env, &l.page[0], val, l.mmu_idx, l.memop, ra);
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return;
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}
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/* Swap to little endian for simplicity, then store by bytes. */
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if ((l.memop & MO_BSWAP) != MO_LE) {
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val = bswap32(val);
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}
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val = do_st_leN(env, &l.page[0], val, l.mmu_idx, ra);
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(void) do_st_leN(env, &l.page[1], val, l.mmu_idx, ra);
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}
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void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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full_le_stl_mmu(env, addr, val, oi, retaddr);
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}
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static void full_be_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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validate_memop(oi, MO_BEUL);
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store_helper(env, addr, val, oi, retaddr, MO_BEUL);
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validate_memop(oi, MO_LEUL);
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do_st4_mmu(env, addr, val, oi, retaddr);
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}
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void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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full_be_stl_mmu(env, addr, val, oi, retaddr);
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validate_memop(oi, MO_BEUL);
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do_st4_mmu(env, addr, val, oi, retaddr);
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}
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|
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static void do_st8_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
MemOpIdx oi, uintptr_t ra)
|
||||
{
|
||||
MMULookupLocals l;
|
||||
bool crosspage;
|
||||
|
||||
crosspage = mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l);
|
||||
if (likely(!crosspage)) {
|
||||
do_st_8(env, &l.page[0], val, l.mmu_idx, l.memop, ra);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Swap to little endian for simplicity, then store by bytes. */
|
||||
if ((l.memop & MO_BSWAP) != MO_LE) {
|
||||
val = bswap64(val);
|
||||
}
|
||||
val = do_st_leN(env, &l.page[0], val, l.mmu_idx, ra);
|
||||
(void) do_st_leN(env, &l.page[1], val, l.mmu_idx, ra);
|
||||
}
|
||||
|
||||
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
validate_memop(oi, MO_LEUQ);
|
||||
store_helper(env, addr, val, oi, retaddr, MO_LEUQ);
|
||||
do_st8_mmu(env, addr, val, oi, retaddr);
|
||||
}
|
||||
|
||||
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
validate_memop(oi, MO_BEUQ);
|
||||
store_helper(env, addr, val, oi, retaddr, MO_BEUQ);
|
||||
do_st8_mmu(env, addr, val, oi, retaddr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Store Helpers for cpu_ldst.h
|
||||
*/
|
||||
|
||||
typedef void FullStoreHelper(CPUArchState *env, target_ulong addr,
|
||||
uint64_t val, MemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
static inline void cpu_store_helper(CPUArchState *env, target_ulong addr,
|
||||
uint64_t val, MemOpIdx oi, uintptr_t ra,
|
||||
FullStoreHelper *full_store)
|
||||
static void plugin_store_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi)
|
||||
{
|
||||
full_store(env, addr, val, oi, ra);
|
||||
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
||||
}
|
||||
|
||||
void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, full_stb_mmu);
|
||||
helper_ret_stb_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, full_be_stw_mmu);
|
||||
helper_be_stw_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, full_be_stl_mmu);
|
||||
helper_be_stl_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, helper_be_stq_mmu);
|
||||
helper_be_stq_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, full_le_stw_mmu);
|
||||
helper_le_stw_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, full_le_stl_mmu);
|
||||
helper_le_stl_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
|
||||
MemOpIdx oi, uintptr_t retaddr)
|
||||
{
|
||||
cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu);
|
||||
helper_le_stq_mmu(env, addr, val, oi, retaddr);
|
||||
plugin_store_cb(env, addr, oi);
|
||||
}
|
||||
|
||||
void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user