target/arm: Enable FEAT_HCX for -cpu max
This feature adds a new register, HCRX_EL2, which controls many of the newer AArch64 features. So far the register is effectively RES0, because none of the new features are done. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220517054850.177016-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -362,6 +362,7 @@ typedef struct CPUArchState {
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uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
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uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
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uint64_t hcr_el2; /* Hypervisor configuration register */
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uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
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uint64_t scr_el3; /* Secure configuration register. */
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union { /* Fault status registers. */
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struct {
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@ -1545,6 +1546,19 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
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#define HCR_TWEDEN (1ULL << 59)
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#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
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#define HCRX_ENAS0 (1ULL << 0)
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#define HCRX_ENALS (1ULL << 1)
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#define HCRX_ENASR (1ULL << 2)
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#define HCRX_FNXS (1ULL << 3)
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#define HCRX_FGTNXS (1ULL << 4)
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#define HCRX_SMPME (1ULL << 5)
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#define HCRX_TALLINT (1ULL << 6)
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#define HCRX_VINMI (1ULL << 7)
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#define HCRX_VFNMI (1ULL << 8)
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#define HCRX_CMOW (1ULL << 9)
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#define HCRX_MCE2 (1ULL << 10)
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#define HCRX_MSCEN (1ULL << 11)
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#define HPFAR_NS (1ULL << 63)
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#define SCR_NS (1U << 0)
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@ -2312,6 +2326,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
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* Not included here is HCR_RW.
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*/
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uint64_t arm_hcr_el2_eff(CPUARMState *env);
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uint64_t arm_hcrx_el2_eff(CPUARMState *env);
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/* Return true if the specified exception level is running in AArch64 state. */
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static inline bool arm_el_is_aa64(CPUARMState *env, int el)
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@ -3933,6 +3948,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
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}
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static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
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}
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static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
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@ -934,6 +934,7 @@ static void aarch64_max_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
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t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
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t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
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t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
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cpu->isar.id_aa64mmfr1 = t;
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t = cpu->isar.id_aa64mmfr2;
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@ -5288,6 +5288,52 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
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return ret;
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}
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static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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uint64_t valid_mask = 0;
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/* No features adding bits to HCRX are implemented. */
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/* Clear RES0 bits. */
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env->cp15.hcrx_el2 = value & valid_mask;
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}
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static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) < 3
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&& arm_feature(env, ARM_FEATURE_EL3)
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&& !(env->cp15.scr_el3 & SCR_HXEN)) {
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return CP_ACCESS_TRAP_EL3;
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}
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return CP_ACCESS_OK;
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}
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static const ARMCPRegInfo hcrx_el2_reginfo = {
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.name = "HCRX_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2,
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.access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen,
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.fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2),
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};
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/* Return the effective value of HCRX_EL2. */
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uint64_t arm_hcrx_el2_eff(CPUARMState *env)
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{
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/*
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* The bits in this register behave as 0 for all purposes other than
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* direct reads of the register if:
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* - EL2 is not enabled in the current security state,
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* - SCR_EL3.HXEn is 0.
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*/
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if (!arm_is_el2_enabled(env)
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|| (arm_feature(env, ARM_FEATURE_EL3)
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&& !(env->cp15.scr_el3 & SCR_HXEN))) {
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return 0;
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}
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return env->cp15.hcrx_el2;
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}
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static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -8405,6 +8451,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, zcr_reginfo);
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}
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if (cpu_isar_feature(aa64_hcx, cpu)) {
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define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo);
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}
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#ifdef TARGET_AARCH64
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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define_arm_cp_regs(cpu, pauth_reginfo);
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