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target-ppc: Optimize rlwnm MB=0 ME=31

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Optimize the special case of rlwnm where MB=0 and ME=31.  This can
be implemented using a ROTL.

Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-08-25 14:25:41 -05:00 committed by Alexander Graf
parent 8979c2f602
commit 57fca134bb
1 changed files with 37 additions and 25 deletions
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62
target-ppc/translate.c
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@ -1721,37 +1721,49 @@ static void gen_rlwinm(DisasContext *ctx)
static void gen_rlwnm(DisasContext *ctx) static void gen_rlwnm(DisasContext *ctx)
{ {
uint32_t mb, me; uint32_t mb, me;
TCGv t0;
#if defined(TARGET_PPC64)
TCGv t1;
#endif
mb = MB(ctx->opcode); mb = MB(ctx->opcode);
me = ME(ctx->opcode); me = ME(ctx->opcode);
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); if (likely(mb == 0 && me == 31)) {
#if defined(TARGET_PPC64) TCGv_i32 t0, t1;
t1 = tcg_temp_new_i64(); t0 = tcg_temp_new_i32();
tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)], t1 = tcg_temp_new_i32();
cpu_gpr[rS(ctx->opcode)], 32, 32); tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
tcg_gen_rotl_i64(t0, t1, t0); tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free_i64(t1); tcg_gen_andi_i32(t0, t0, 0x1f);
#else tcg_gen_rotl_i32(t1, t1, t0);
tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
#endif tcg_temp_free_i32(t0);
if (unlikely(mb != 0 || me != 31)) { tcg_temp_free_i32(t1);
#if defined(TARGET_PPC64)
mb += 32;
me += 32;
#endif
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
} else { } else {
TCGv t0;
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
tcg_gen_andi_tl(t0, t0, MASK(32, 63)); TCGv t1;
#endif #endif
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
#if defined(TARGET_PPC64)
t1 = tcg_temp_new_i64();
tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)], 32, 32);
tcg_gen_rotl_i64(t0, t1, t0);
tcg_temp_free_i64(t1);
#else
tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
#endif
if (unlikely(mb != 0 || me != 31)) {
#if defined(TARGET_PPC64)
mb += 32;
me += 32;
#endif
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
} else {
tcg_gen_andi_tl(t0, t0, MASK(32, 63));
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
}
tcg_temp_free(t0);
} }
tcg_temp_free(t0);
if (unlikely(Rc(ctx->opcode) != 0)) if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
} }