aspeed/sdmc: Allow writes to unprotected registers
A subset of registers are not protected by the lock behaviour, so allow unconditionally writing to those. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20200819100956.2216690-18-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -33,15 +33,28 @@
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/* Configuration Register */
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#define R_CONF (0x04 / 4)
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/* Interrupt control/status */
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#define R_ISR (0x50 / 4)
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/* Control/Status Register #1 (ast2500) */
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#define R_STATUS1 (0x60 / 4)
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#define PHY_BUSY_STATE BIT(0)
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#define PHY_PLL_LOCK_STATUS BIT(4)
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/* Reserved */
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#define R_MCR6C (0x6c / 4)
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#define R_ECC_TEST_CTRL (0x70 / 4)
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#define ECC_TEST_FINISHED BIT(12)
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#define ECC_TEST_FAIL BIT(13)
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#define R_TEST_START_LEN (0x74 / 4)
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#define R_TEST_FAIL_DQ (0x78 / 4)
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#define R_TEST_INIT_VAL (0x7c / 4)
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#define R_DRAM_SW (0x88 / 4)
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#define R_DRAM_TIME (0x8c / 4)
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#define R_ECC_ERR_INJECT (0xb4 / 4)
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/*
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* Configuration register Ox4 (for Aspeed AST2400 SOC)
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*
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@ -449,6 +462,20 @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
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static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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uint32_t data)
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{
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/* Unprotected registers */
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switch (reg) {
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case R_ISR:
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case R_MCR6C:
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case R_TEST_START_LEN:
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case R_TEST_FAIL_DQ:
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case R_TEST_INIT_VAL:
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case R_DRAM_SW:
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case R_DRAM_TIME:
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case R_ECC_ERR_INJECT:
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s->regs[reg] = data;
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return;
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}
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if (s->regs[R_PROT] == PROT_HARDLOCKED) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",
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__func__);
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