mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target-alpha: fix locked loads/stores

Browse Source 
Fix reading of cpu_lock in gen_qemu_stql_c, original patch from Laurent
Desnogues.

A new flag was added to gen_store_mem to allocate local temps instead
of temps;  this flag should be set when the tcg_gen_qemu_store callback
uses brcond before using the temps or else liveness analysis will get
rid of the temps.

This also adds lock printing in cpu_dump_state which can help
debug.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5645 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-11-07 14:00:24 +00:00
parent e32ad5c268
commit 57a92c8e36
2 changed files with 22 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target-alpha/helper.c
View File

@ -434,5 +434,6 @@ void cpu_dump_state (CPUState *env, FILE *f,
if ((i % 3) == 2) if ((i % 3) == 2)
cpu_fprintf(f, "\n"); cpu_fprintf(f, "\n");
} }
cpu_fprintf(f, "\nlock " TARGET_FMT_lx "\n", env->lock);
} }

34
target-alpha/translate.c
View File

@ -234,9 +234,13 @@ static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
static always_inline void gen_store_mem (DisasContext *ctx, static always_inline void gen_store_mem (DisasContext *ctx,
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
int ra, int rb, int32_t disp16, int ra, int rb, int32_t disp16,
int fp, int clear) int fp, int clear, int local)
{ {
TCGv addr = tcg_temp_new(TCG_TYPE_I64); TCGv addr = tcg_temp_new(TCG_TYPE_I64);
if (local)
addr = tcg_temp_local_new(TCG_TYPE_I64);
else
addr = tcg_temp_new(TCG_TYPE_I64);
if (rb != 31) { if (rb != 31) {
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
if (clear) if (clear)
@ -252,7 +256,11 @@ static always_inline void gen_store_mem (DisasContext *ctx,
else else
tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
} else { } else {
TCGv zero = tcg_const_i64(0); TCGv zero;
if (local)
zero = tcg_const_local_i64(0);
else
zero = tcg_const_i64(0);
tcg_gen_qemu_store(zero, addr, ctx->mem_idx); tcg_gen_qemu_store(zero, addr, ctx->mem_idx);
tcg_temp_free(zero); tcg_temp_free(zero);
} }
@ -636,15 +644,15 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x0D: case 0x0D:
/* STW */ /* STW */
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0);
break; break;
case 0x0E: case 0x0E:
/* STB */ /* STB */
gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0);
break; break;
case 0x0F: case 0x0F:
/* STQ_U */ /* STQ_U */
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0);
break; break;
case 0x10: case 0x10:
switch (fn7) { switch (fn7) {
@ -2090,19 +2098,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x24: case 0x24:
/* STF */ /* STF */
gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0);
break; break;
case 0x25: case 0x25:
/* STG */ /* STG */
gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0);
break; break;
case 0x26: case 0x26:
/* STS */ /* STS */
gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0);
break; break;
case 0x27: case 0x27:
/* STT */ /* STT */
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0);
break; break;
case 0x28: case 0x28:
/* LDL */ /* LDL */
@ -2122,19 +2130,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
break; break;
case 0x2C: case 0x2C:
/* STL */ /* STL */
gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0);
break; break;
case 0x2D: case 0x2D:
/* STQ */ /* STQ */
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0);
break; break;
case 0x2E: case 0x2E:
/* STL_C */ /* STL_C */
gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1);
break; break;
case 0x2F: case 0x2F:
/* STQ_C */ /* STQ_C */
gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1);
break; break;
case 0x30: case 0x30:
/* BR */ /* BR */