target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx
We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb. Flush the tlb when invalidating stage 1+2 translations. Re-use alle1_tlbmask() for other instances of EL1&0 + Stage2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20221011031911.2408754-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
a1ce3084c5
commit
575a94af3c
@ -45,6 +45,6 @@
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bool guarded;
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#endif
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#define NB_MMU_MODES 10
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#define NB_MMU_MODES 12
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#endif
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@ -2906,8 +2906,9 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
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* EL2 (aka NS PL2)
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* EL3 (aka S PL1)
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* Physical (NS & S)
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* Stage2 (NS & S)
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*
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* for a total of 10 different mmu_idx.
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* for a total of 12 different mmu_idx.
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*
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* R profile CPUs have an MPU, but can use the same set of MMU indexes
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* as A profile. They only need to distinguish EL0 and EL1 (and
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@ -2976,6 +2977,15 @@ typedef enum ARMMMUIdx {
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ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A,
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ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A,
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/*
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* Used for second stage of an S12 page table walk, or for descriptor
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* loads during first stage of an S1 page table walk. Note that both
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* are in use simultaneously for SecureEL2: the security state for
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* the S2 ptw is selected by the NS bit from the S1 ptw.
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*/
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ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A,
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ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A,
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/*
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* These are not allocated TLBs and are used only for AT system
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* instructions or for the first stage of an S12 page table walk.
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@ -2983,15 +2993,6 @@ typedef enum ARMMMUIdx {
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ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
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ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
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ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
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/*
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* Not allocated a TLB: used only for second stage of an S12 page
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* table walk, or for descriptor loads during first stage of an S1
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* page table walk. Note that if we ever want to have a TLB for this
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* then various TLB flush insns which currently are no-ops or flush
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* only stage 1 MMU indexes will need to change to flush stage 2.
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*/
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ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
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ARMMMUIdx_Stage2_S = 4 | ARM_MMU_IDX_NOTLB,
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/*
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* M-profile.
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@ -3022,6 +3023,8 @@ typedef enum ARMMMUIdxBit {
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TO_CORE_BIT(E20_2),
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TO_CORE_BIT(E20_2_PAN),
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TO_CORE_BIT(E3),
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TO_CORE_BIT(Stage2),
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TO_CORE_BIT(Stage2_S),
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TO_CORE_BIT(MUser),
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TO_CORE_BIT(MPriv),
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@ -399,6 +399,21 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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raw_write(env, ri, value);
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}
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static int alle1_tlbmask(CPUARMState *env)
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{
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/*
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* Note that the 'ALL' scope must invalidate both stage 1 and
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* stage 2 translations, whereas most other scopes only invalidate
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* stage 1 translations.
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*/
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return (ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0 |
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ARMMMUIdxBit_Stage2 |
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ARMMMUIdxBit_Stage2_S);
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}
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/* IS variants of TLB operations must affect all cores */
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static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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@ -501,10 +516,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx(cs,
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ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0);
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tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
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}
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static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -512,10 +524,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs,
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ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env));
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}
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@ -554,6 +563,24 @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMMMUIdxBit_E2);
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}
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static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12;
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tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
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}
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static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12;
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2);
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}
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static const ARMCPRegInfo cp_reginfo[] = {
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/* Define the secure and non-secure FCSE identifier CP registers
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* separately because there is no secure bank in V8 (no _EL3). This allows
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@ -3786,13 +3813,10 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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/*
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* A change in VMID to the stage2 page table (Stage2) invalidates
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* the combined stage 1&2 tlbs (EL10_1 and EL10_0).
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* the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
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*/
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if (raw_read(env, ri) != value) {
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uint16_t mask = ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0;
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tlb_flush_by_mmuidx(cs, mask);
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tlb_flush_by_mmuidx(cs, alle1_tlbmask(env));
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raw_write(env, ri, value);
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}
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}
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@ -4313,18 +4337,6 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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}
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static int alle1_tlbmask(CPUARMState *env)
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{
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/*
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* Note that the 'ALL' scope must invalidate both stage 1 and
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* stage 2 translations, whereas most other scopes only invalidate
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* stage 1 translations.
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*/
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return (ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0);
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}
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static int e2_tlbmask(CPUARMState *env)
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{
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return (ARMMMUIdxBit_E20_0 |
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@ -4467,6 +4479,43 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMMMUIdxBit_E3, bits);
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}
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static int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
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{
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/*
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* The MSB of value is the NS field, which only applies if SEL2
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* is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
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*/
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return (value >= 0
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&& cpu_isar_feature(aa64_sel2, env_archcpu(env))
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&& arm_is_secure_below_el3(env)
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? ARMMMUIdxBit_Stage2_S
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: ARMMMUIdxBit_Stage2);
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}
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static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = ipas2e1_tlbmask(env, value);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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if (tlb_force_broadcast(env)) {
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
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} else {
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tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
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}
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}
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static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = ipas2e1_tlbmask(env, value);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
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}
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#ifdef TARGET_AARCH64
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typedef struct {
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uint64_t base;
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@ -4652,6 +4701,20 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
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do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
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}
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static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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do_rvae_write(env, value, ipas2e1_tlbmask(env, value),
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tlb_force_broadcast(env));
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}
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static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true);
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}
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#endif
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static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -4930,10 +4993,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.writefn = tlbi_aa64_vae1_write },
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{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ipas2e1is_write },
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{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ipas2e1is_write },
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{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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@ -4944,10 +5009,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.writefn = tlbi_aa64_alle1is_write },
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{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ipas2e1_write },
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{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ipas2e1_write },
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{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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@ -5028,16 +5095,20 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.writefn = tlbimva_hyp_is_write },
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{ .name = "TLBIIPAS2",
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.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL2_W },
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.type = ARM_CP_NO_RAW, .access = PL2_W,
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.writefn = tlbiipas2_hyp_write },
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{ .name = "TLBIIPAS2IS",
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.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
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.type = ARM_CP_NOP, .access = PL2_W },
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.type = ARM_CP_NO_RAW, .access = PL2_W,
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.writefn = tlbiipas2is_hyp_write },
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{ .name = "TLBIIPAS2L",
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.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
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.type = ARM_CP_NOP, .access = PL2_W },
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.type = ARM_CP_NO_RAW, .access = PL2_W,
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.writefn = tlbiipas2_hyp_write },
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{ .name = "TLBIIPAS2LIS",
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.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
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.type = ARM_CP_NOP, .access = PL2_W },
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.type = ARM_CP_NO_RAW, .access = PL2_W,
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.writefn = tlbiipas2is_hyp_write },
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/* 32 bit cache operations */
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{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
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.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
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@ -6694,10 +6765,12 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ripas2e1is_write },
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{ .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ripas2e1is_write },
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{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
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@ -6708,10 +6781,12 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
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.writefn = tlbi_aa64_rvae2is_write },
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{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
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.access = PL2_W, .type = ARM_CP_NOP },
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{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ripas2e1_write },
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{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
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.access = PL2_W, .type = ARM_CP_NOP },
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_ripas2e1_write },
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{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
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