ppc/ppc405: Activate MMU logs
There is no need to deactivate MMU logging at compile time. Remove all use of defines. Only keep DUMP_PAGE_TABLES for another series since page tables could be dumped from the monitor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
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56964585a0
@ -34,29 +34,7 @@
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#include "mmu-book3s-v3.h"
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#include "mmu-radix64.h"
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/* #define DEBUG_MMU */
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/* #define DEBUG_BATS */
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/* #define DEBUG_SOFTWARE_TLB */
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/* #define DUMP_PAGE_TABLES */
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/* #define FLUSH_ALL_TLBS */
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#ifdef DEBUG_MMU
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# define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0)
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#else
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# define LOG_MMU_STATE(cpu) do { } while (0)
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#endif
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#ifdef DEBUG_SOFTWARE_TLB
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# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
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#else
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# define LOG_SWTLB(...) do { } while (0)
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#endif
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#ifdef DEBUG_BATS
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# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
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#else
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# define LOG_BATS(...) do { } while (0)
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#endif
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void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
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{
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@ -231,18 +209,20 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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tlb = &env->tlb.tlb6[nr];
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/* This test "emulates" the PTE index match for hardware TLBs */
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if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
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LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
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"] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
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qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s [" TARGET_FMT_lx
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" " TARGET_FMT_lx "] <> " TARGET_FMT_lx "\n",
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nr, env->nb_tlb,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
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continue;
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}
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LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
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TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, eaddr, tlb->pte1,
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access_type == MMU_DATA_STORE ? 'S' : 'L',
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access_type == MMU_INST_FETCH ? 'I' : 'D');
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qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s " TARGET_FMT_lx " <> "
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TARGET_FMT_lx " " TARGET_FMT_lx " %c %c\n",
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nr, env->nb_tlb,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, eaddr, tlb->pte1,
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access_type == MMU_DATA_STORE ? 'S' : 'L',
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access_type == MMU_INST_FETCH ? 'I' : 'D');
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switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1,
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0, access_type)) {
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case -3:
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@ -272,8 +252,9 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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}
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if (best != -1) {
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done:
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LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx
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" prot=%01x ret=%d\n",
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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/* Update page flags */
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pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, access_type);
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}
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@ -317,7 +298,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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int ret = -1;
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bool ifetch = access_type == MMU_INST_FETCH;
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LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
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qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
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ifetch ? 'I' : 'D', virtual);
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if (ifetch) {
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BATlt = env->IBAT[1];
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@ -332,9 +313,9 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n", __func__,
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ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
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qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
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TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
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ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
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if ((virtual & 0xF0000000) == BEPIu &&
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((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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/* BAT matches */
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@ -347,32 +328,33 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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ctx->prot = prot;
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ret = check_prot(ctx->prot, access_type);
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if (ret == 0) {
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LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " TARGET_FMT_plx
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" prot=%c%c\n", i, ctx->raddr,
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ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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}
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break;
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}
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}
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}
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if (ret < 0) {
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#if defined(DEBUG_BATS)
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if (qemu_log_enabled()) {
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LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
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qemu_log_mask(CPU_LOG_MMU, "no BAT match for "
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TARGET_FMT_lx ":\n", virtual);
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & 0xF0000000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
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TARGET_FMT_lx " " TARGET_FMT_lx "\n",
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__func__, ifetch ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v "
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TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
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TARGET_FMT_lx " " TARGET_FMT_lx "\n",
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__func__, ifetch ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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}
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}
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#endif
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}
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/* No hit */
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return ret;
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@ -401,11 +383,12 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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vsid = sr & 0x00FFFFFF;
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target_page_bits = TARGET_PAGE_BITS;
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qemu_log_mask(CPU_LOG_MMU,
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"Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx
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" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0, access_type == MMU_DATA_STORE, type);
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"Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx
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" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
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" ir=%d dr=%d pr=%d %d t=%d\n",
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eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
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(int)msr_dr, pr != 0 ? 1 : 0,
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access_type == MMU_DATA_STORE, type);
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
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hash = vsid ^ pgidx;
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ctx->ptem = (vsid << 7) | (pgidx >> 10);
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@ -536,9 +519,10 @@ int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
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return -1;
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}
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mask = ~(tlb->size - 1);
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LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
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" " TARGET_FMT_lx " %u %x\n", __func__, i, address, pid, tlb->EPN,
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mask, (uint32_t)tlb->PID, tlb->prot);
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qemu_log_mask(CPU_LOG_MMU, "%s: TLB %d address " TARGET_FMT_lx
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" PID %u <=> " TARGET_FMT_lx " " TARGET_FMT_lx " %u %x\n",
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__func__, i, address, pid, tlb->EPN,
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mask, (uint32_t)tlb->PID, tlb->prot);
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/* Check PID */
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if (tlb->PID != 0 && tlb->PID != pid) {
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return -1;
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@ -575,8 +559,9 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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}
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zsel = (tlb->attr >> 4) & 0xF;
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zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
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LOG_SWTLB("%s: TLB %d zsel %d zpr %d ty %d attr %08x\n",
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__func__, i, zsel, zpr, access_type, tlb->attr);
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qemu_log_mask(CPU_LOG_MMU,
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"%s: TLB %d zsel %d zpr %d ty %d attr %08x\n",
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__func__, i, zsel, zpr, access_type, tlb->attr);
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/* Check execute enable bit */
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switch (zpr) {
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case 0x2:
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@ -610,14 +595,16 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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}
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if (ret >= 0) {
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ctx->raddr = raddr;
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LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
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" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
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ret);
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qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
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" => " TARGET_FMT_plx
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" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
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ret);
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return 0;
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}
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}
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LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
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" %d %d\n", __func__, address, raddr, ctx->prot, ret);
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qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
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" => " TARGET_FMT_plx
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" %d %d\n", __func__, address, raddr, ctx->prot, ret);
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return ret;
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}
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@ -646,7 +633,7 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
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goto found_tlb;
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}
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LOG_SWTLB("%s: TLB entry not found\n", __func__);
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qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__);
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return -1;
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found_tlb:
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@ -659,17 +646,17 @@ found_tlb:
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/* Check the address space */
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if ((access_type == MMU_INST_FETCH ? msr_ir : msr_dr) != (tlb->attr & 1)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
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return -1;
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}
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*prot = prot2;
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if (prot2 & prot_for_access_type(access_type)) {
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LOG_SWTLB("%s: good TLB!\n", __func__);
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qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
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return 0;
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}
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LOG_SWTLB("%s: no prot match: %x\n", __func__, prot2);
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qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, prot2);
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return access_type == MMU_INST_FETCH ? -3 : -2;
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}
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@ -694,12 +681,13 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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if (ret >= 0) {
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ctx->raddr = raddr;
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LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
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" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
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ret);
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qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
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" => " TARGET_FMT_plx " %d %d\n", __func__,
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address, ctx->raddr, ctx->prot, ret);
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} else {
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LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
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" %d %d\n", __func__, address, raddr, ctx->prot, ret);
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qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
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" => " TARGET_FMT_plx " %d %d\n", __func__,
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address, raddr, ctx->prot, ret);
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}
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return ret;
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@ -734,10 +722,11 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
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}
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mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
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LOG_SWTLB("%s: TLB ADDR=0x" TARGET_FMT_lx " PID=0x%x MAS1=0x%x MAS2=0x%"
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PRIx64 " mask=0x%" HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%"
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PRIx32 "\n", __func__, address, pid, tlb->mas1, tlb->mas2, mask,
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tlb->mas7_3, tlb->mas8);
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qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx
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" PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%"
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HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n",
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__func__, address, pid, tlb->mas1, tlb->mas2, mask,
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tlb->mas7_3, tlb->mas8);
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/* Check PID */
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tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT;
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@ -838,7 +827,7 @@ static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
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}
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}
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LOG_SWTLB("%s: TLB entry not found\n", __func__);
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qemu_log_mask(CPU_LOG_MMU, "%s: TLB entry not found\n", __func__);
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return -1;
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found_tlb:
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@ -873,17 +862,17 @@ found_tlb:
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}
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if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
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LOG_SWTLB("%s: AS doesn't match\n", __func__);
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qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
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return -1;
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}
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*prot = prot2;
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if (prot2 & prot_for_access_type(access_type)) {
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LOG_SWTLB("%s: good TLB!\n", __func__);
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qemu_log_mask(CPU_LOG_MMU, "%s: good TLB!\n", __func__);
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return 0;
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}
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LOG_SWTLB("%s: no prot match: %x\n", __func__, prot2);
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qemu_log_mask(CPU_LOG_MMU, "%s: no prot match: %x\n", __func__, prot2);
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return access_type == MMU_INST_FETCH ? -3 : -2;
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}
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@ -919,12 +908,13 @@ found_tlb:
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if (ret >= 0) {
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ctx->raddr = raddr;
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LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
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" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
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ret);
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qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
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" => " TARGET_FMT_plx " %d %d\n", __func__, address,
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ctx->raddr, ctx->prot, ret);
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} else {
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LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
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" %d %d\n", __func__, address, raddr, ctx->prot, ret);
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qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
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" => " TARGET_FMT_plx " %d %d\n", __func__, address,
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raddr, ctx->prot, ret);
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}
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return ret;
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@ -1338,7 +1328,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
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}
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if (guest_visible) {
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LOG_MMU_STATE(cs);
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log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
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if (type == ACCESS_CODE) {
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switch (ret) {
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case -1:
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@ -36,23 +36,8 @@
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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/* #define DEBUG_BATS */
|
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/* #define DEBUG_SOFTWARE_TLB */
|
||||
/* #define DUMP_PAGE_TABLES */
|
||||
/* #define FLUSH_ALL_TLBS */
|
||||
|
||||
#ifdef DEBUG_SOFTWARE_TLB
|
||||
# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
|
||||
#else
|
||||
# define LOG_SWTLB(...) do { } while (0)
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_BATS
|
||||
# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
|
||||
#else
|
||||
# define LOG_BATS(...) do { } while (0)
|
||||
#endif
|
||||
|
||||
/*****************************************************************************/
|
||||
/* PowerPC MMU emulation */
|
||||
|
||||
@ -89,8 +74,8 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
|
||||
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
|
||||
tlb = &env->tlb.tlb6[nr];
|
||||
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
|
||||
LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
|
||||
env->nb_tlb, eaddr);
|
||||
qemu_log_mask(CPU_LOG_MMU, "TLB invalidate %d/%d "
|
||||
TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr);
|
||||
pte_invalidate(&tlb->pte0);
|
||||
tlb_flush_page(cs, tlb->EPN);
|
||||
}
|
||||
@ -115,8 +100,9 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
|
||||
|
||||
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
|
||||
tlb = &env->tlb.tlb6[nr];
|
||||
LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
|
||||
" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
|
||||
qemu_log_mask(CPU_LOG_MMU, "Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 "
|
||||
TARGET_FMT_lx " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb,
|
||||
EPN, pte0, pte1);
|
||||
/* Invalidate any pending reference in QEMU for this virtual address */
|
||||
ppc6xx_tlb_invalidate_virt2(env, EPN, is_code, 1);
|
||||
tlb->pte0 = pte0;
|
||||
@ -204,25 +190,27 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
|
||||
end = base + mask + 0x00020000;
|
||||
if (((end - base) >> TARGET_PAGE_BITS) > 1024) {
|
||||
/* Flushing 1024 4K pages is slower than a complete flush */
|
||||
LOG_BATS("Flush all BATs\n");
|
||||
qemu_log_mask(CPU_LOG_MMU, "Flush all BATs\n");
|
||||
tlb_flush(cs);
|
||||
LOG_BATS("Flush done\n");
|
||||
qemu_log_mask(CPU_LOG_MMU, "Flush done\n");
|
||||
return;
|
||||
}
|
||||
LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
|
||||
TARGET_FMT_lx ")\n", base, end, mask);
|
||||
qemu_log_mask(CPU_LOG_MMU, "Flush BAT from " TARGET_FMT_lx
|
||||
" to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n",
|
||||
base, end, mask);
|
||||
for (page = base; page != end; page += TARGET_PAGE_SIZE) {
|
||||
tlb_flush_page(cs, page);
|
||||
}
|
||||
LOG_BATS("Flush done\n");
|
||||
qemu_log_mask(CPU_LOG_MMU, "Flush done\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
|
||||
target_ulong value)
|
||||
{
|
||||
LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
|
||||
nr, ul == 0 ? 'u' : 'l', value, env->nip);
|
||||
qemu_log_mask(CPU_LOG_MMU, "Set %cBAT%d%c to " TARGET_FMT_lx " ("
|
||||
TARGET_FMT_lx ")\n", ID, nr, ul == 0 ? 'u' : 'l',
|
||||
value, env->nip);
|
||||
}
|
||||
|
||||
void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value)
|
||||
@ -550,9 +538,9 @@ static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code)
|
||||
}
|
||||
way = (env->spr[SPR_SRR1] >> 17) & 1;
|
||||
(void)EPN; /* avoid a compiler warning */
|
||||
LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
|
||||
" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
|
||||
RPN, way);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx
|
||||
" PTE0 " TARGET_FMT_lx " PTE1 " TARGET_FMT_lx " way %d\n",
|
||||
__func__, new_EPN, EPN, CMP, RPN, way);
|
||||
/* Store this TLB */
|
||||
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
|
||||
way, is_code, CMP, RPN);
|
||||
@ -721,15 +709,17 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
|
||||
ppcemb_tlb_t *tlb;
|
||||
target_ulong page, end;
|
||||
|
||||
LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s entry %d val " TARGET_FMT_lx "\n",
|
||||
__func__, (int)entry,
|
||||
val);
|
||||
entry &= PPC4XX_TLB_ENTRY_MASK;
|
||||
tlb = &env->tlb.tlbe[entry];
|
||||
/* Invalidate previous TLB (if it's valid) */
|
||||
if (tlb->prot & PAGE_VALID) {
|
||||
end = tlb->EPN + tlb->size;
|
||||
LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
|
||||
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start "
|
||||
TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
|
||||
(int)entry, tlb->EPN, end);
|
||||
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
|
||||
tlb_flush_page(cs, page);
|
||||
}
|
||||
@ -758,18 +748,20 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
|
||||
tlb->prot &= ~PAGE_VALID;
|
||||
}
|
||||
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
|
||||
LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
|
||||
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
|
||||
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
|
||||
tlb->prot & PAGE_READ ? 'r' : '-',
|
||||
tlb->prot & PAGE_WRITE ? 'w' : '-',
|
||||
tlb->prot & PAGE_EXEC ? 'x' : '-',
|
||||
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
|
||||
" EPN " TARGET_FMT_lx " size " TARGET_FMT_lx
|
||||
" prot %c%c%c%c PID %d\n", __func__,
|
||||
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
|
||||
tlb->prot & PAGE_READ ? 'r' : '-',
|
||||
tlb->prot & PAGE_WRITE ? 'w' : '-',
|
||||
tlb->prot & PAGE_EXEC ? 'x' : '-',
|
||||
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
|
||||
/* Invalidate new TLB (if valid) */
|
||||
if (tlb->prot & PAGE_VALID) {
|
||||
end = tlb->EPN + tlb->size;
|
||||
LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
|
||||
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s: invalidate TLB %d start "
|
||||
TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
|
||||
(int)entry, tlb->EPN, end);
|
||||
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
|
||||
tlb_flush_page(cs, page);
|
||||
}
|
||||
@ -781,8 +773,8 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
|
||||
{
|
||||
ppcemb_tlb_t *tlb;
|
||||
|
||||
LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,
|
||||
val);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s entry %i val " TARGET_FMT_lx "\n",
|
||||
__func__, (int)entry, val);
|
||||
entry &= PPC4XX_TLB_ENTRY_MASK;
|
||||
tlb = &env->tlb.tlbe[entry];
|
||||
tlb->attr = val & PPC4XX_TLBLO_ATTR_MASK;
|
||||
@ -794,13 +786,14 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
|
||||
if (val & PPC4XX_TLBLO_WR) {
|
||||
tlb->prot |= PAGE_WRITE;
|
||||
}
|
||||
LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
|
||||
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
|
||||
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
|
||||
tlb->prot & PAGE_READ ? 'r' : '-',
|
||||
tlb->prot & PAGE_WRITE ? 'w' : '-',
|
||||
tlb->prot & PAGE_EXEC ? 'x' : '-',
|
||||
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
|
||||
" EPN " TARGET_FMT_lx
|
||||
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
|
||||
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
|
||||
tlb->prot & PAGE_READ ? 'r' : '-',
|
||||
tlb->prot & PAGE_WRITE ? 'w' : '-',
|
||||
tlb->prot & PAGE_EXEC ? 'x' : '-',
|
||||
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
|
||||
}
|
||||
|
||||
target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
|
||||
@ -816,8 +809,8 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
|
||||
target_ulong EPN, RPN, size;
|
||||
int do_flush_tlbs;
|
||||
|
||||
LOG_SWTLB("%s word %d entry %d value " TARGET_FMT_lx "\n",
|
||||
__func__, word, (int)entry, value);
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s word %d entry %d value " TARGET_FMT_lx "\n",
|
||||
__func__, word, (int)entry, value);
|
||||
do_flush_tlbs = 0;
|
||||
entry &= 0x3F;
|
||||
tlb = &env->tlb.tlbe[entry];
|
||||
|
Loading…
Reference in New Issue
Block a user