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riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

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Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.

Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:19:58 -07:00 committed by Palmer Dabbelt
parent 9baa9f7c9f
commit 56449d20e9
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
5 changed files with 111 additions and 114 deletions
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2
hw/riscv/Makefile.objs
View File

@ -2,9 +2,9 @@ obj-y += boot.o
obj-$(CONFIG_SPIKE) += riscv_htif.o
obj-$(CONFIG_HART) += riscv_hart.o
obj-$(CONFIG_SIFIVE_E) += sifive_e.o
obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o
obj-$(CONFIG_SIFIVE) += sifive_clint.o
obj-$(CONFIG_SIFIVE) += sifive_gpio.o
obj-$(CONFIG_SIFIVE) += sifive_prci.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
obj-$(CONFIG_SIFIVE_U) += sifive_u.o

4
hw/riscv/sifive_e.c
View File

@ -40,9 +40,9 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/sifive_e_prci.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
/* GPIO */

77
hw/riscv/sifive_prci.c → hw/riscv/sifive_e_prci.c
View File

@ -1,5 +1,5 @@
/*
* QEMU SiFive PRCI (Power, Reset, Clock, Interrupt)
* QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt)
*
* Copyright (c) 2017 SiFive, Inc.
*
@ -23,19 +23,19 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_e_prci.h"
static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFivePRCIState *s = opaque;
SiFiveEPRCIState *s = opaque;
switch (addr) {
case SIFIVE_PRCI_HFROSCCFG:
case SIFIVE_E_PRCI_HFROSCCFG:
return s->hfrosccfg;
case SIFIVE_PRCI_HFXOSCCFG:
case SIFIVE_E_PRCI_HFXOSCCFG:
return s->hfxosccfg;
case SIFIVE_PRCI_PLLCFG:
case SIFIVE_E_PRCI_PLLCFG:
return s->pllcfg;
case SIFIVE_PRCI_PLLOUTDIV:
case SIFIVE_E_PRCI_PLLOUTDIV:
return s->plloutdiv;
}
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
@ -43,27 +43,27 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
return 0;
}
static void sifive_prci_write(void *opaque, hwaddr addr,
static void sifive_e_prci_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
SiFivePRCIState *s = opaque;
SiFiveEPRCIState *s = opaque;
switch (addr) {
case SIFIVE_PRCI_HFROSCCFG:
case SIFIVE_E_PRCI_HFROSCCFG:
s->hfrosccfg = (uint32_t) val64;
/* OSC stays ready */
s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY;
s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY;
break;
case SIFIVE_PRCI_HFXOSCCFG:
case SIFIVE_E_PRCI_HFXOSCCFG:
s->hfxosccfg = (uint32_t) val64;
/* OSC stays ready */
s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY;
break;
case SIFIVE_PRCI_PLLCFG:
case SIFIVE_E_PRCI_PLLCFG:
s->pllcfg = (uint32_t) val64;
/* PLL stays locked */
s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK;
s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK;
break;
case SIFIVE_PRCI_PLLOUTDIV:
case SIFIVE_E_PRCI_PLLOUTDIV:
s->plloutdiv = (uint32_t) val64;
break;
default:
@ -72,9 +72,9 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
}
}
static const MemoryRegionOps sifive_prci_ops = {
.read = sifive_prci_read,
.write = sifive_prci_write,
static const MemoryRegionOps sifive_e_prci_ops = {
.read = sifive_e_prci_read,
.write = sifive_e_prci_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
@ -82,43 +82,42 @@ static const MemoryRegionOps sifive_prci_ops = {
}
};
static void sifive_prci_init(Object *obj)
static void sifive_e_prci_init(Object *obj)
{
SiFivePRCIState *s = SIFIVE_PRCI(obj);
SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj);
memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
TYPE_SIFIVE_PRCI, 0x8000);
memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s,
TYPE_SIFIVE_E_PRCI, 0x8000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
SIFIVE_PRCI_PLLCFG_LOCK);
s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
s->hfxosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
SIFIVE_E_PRCI_PLLCFG_LOCK);
s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
}
static const TypeInfo sifive_prci_info = {
.name = TYPE_SIFIVE_PRCI,
static const TypeInfo sifive_e_prci_info = {
.name = TYPE_SIFIVE_E_PRCI,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SiFivePRCIState),
.instance_init = sifive_prci_init,
.instance_size = sizeof(SiFiveEPRCIState),
.instance_init = sifive_e_prci_init,
};
static void sifive_prci_register_types(void)
static void sifive_e_prci_register_types(void)
{
type_register_static(&sifive_prci_info);
type_register_static(&sifive_e_prci_info);
}
type_init(sifive_prci_register_types)
type_init(sifive_e_prci_register_types)
/*
* Create PRCI device.
*/
DeviceState *sifive_prci_create(hwaddr addr)
DeviceState *sifive_e_prci_create(hwaddr addr)
{
DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI);
DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
return dev;

69
include/hw/riscv/sifive_e_prci.h Normal file
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@ -0,0 +1,69 @@
/*
* QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_E_PRCI_H
#define HW_SIFIVE_E_PRCI_H
enum {
SIFIVE_E_PRCI_HFROSCCFG = 0x0,
SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
SIFIVE_E_PRCI_PLLCFG = 0x8,
SIFIVE_E_PRCI_PLLOUTDIV = 0xC
};
enum {
SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
};
enum {
SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
#define SIFIVE_E_PRCI(obj) \
OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI)
typedef struct SiFiveEPRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfrosccfg;
uint32_t hfxosccfg;
uint32_t pllcfg;
uint32_t plloutdiv;
} SiFiveEPRCIState;
DeviceState *sifive_e_prci_create(hwaddr addr);
#endif

71
include/hw/riscv/sifive_prci.h
View File

@ -1,71 +0,0 @@
/*
* QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface
*
* Copyright (c) 2017 SiFive, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_SIFIVE_PRCI_H
#define HW_SIFIVE_PRCI_H
#include "hw/sysbus.h"
enum {
SIFIVE_PRCI_HFROSCCFG = 0x0,
SIFIVE_PRCI_HFXOSCCFG = 0x4,
SIFIVE_PRCI_PLLCFG = 0x8,
SIFIVE_PRCI_PLLOUTDIV = 0xC
};
enum {
SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31),
SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31),
SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30)
};
enum {
SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16),
SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17),
SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18),
SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31)
};
enum {
SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
#define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
#define SIFIVE_PRCI(obj) \
OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI)
typedef struct SiFivePRCIState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion mmio;
uint32_t hfrosccfg;
uint32_t hfxosccfg;
uint32_t pllcfg;
uint32_t plloutdiv;
} SiFivePRCIState;
DeviceState *sifive_prci_create(hwaddr addr);
#endif